1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 08 February 2019 Pages: 1 - 2

2. New Editors – 2019

   Announcement 10 January 2019 Pages: 3 - 4

   

3. 2018 JETTA Reviewers

   Announcement 23 January 2019 Pages: 5 - 6

4. Test Technology Newsletter

   News 08 January 2019 Pages: 7 - 8

   

5. Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

   • Paulo R. C. Villa
   • Rodrigo Travessini
   • Eduardo A. Bezerra

   OriginalPaper 04 February 2019 Pages: 9 - 27

   

6. RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

   • Serhiy Avramenko
   • Massimo Violante

   OriginalPaper 01 February 2019 Pages: 29 - 44

   

7. An Optimized NS2 Module for UHF Passive RFID Systems

   • Rahma Benfraj
   • Vincent Beroulle
   • Aref Meddeb

   OriginalPaper 12 December 2018 Pages: 45 - 58

   

8. Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

   • Amit Karel
   • Florence Azaïs
   • Michel Renovell

   OriginalPaper 02 February 2019 Pages: 59 - 75

   

9. Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

   • Shakeel Ahmad
   • Jerzy Dąbrowski

   OriginalPaper 15 February 2019 Pages: 77 - 85

   

10. An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

    • Andres Gomez
    • Victor Champac

    OriginalPaper 22 January 2019 Pages: 87 - 100

    

11. Metric-Driven Verification Methodology with Regression Management

    • Marek Cieplucha

    OriginalPaper Open access 13 February 2019 Pages: 101 - 110

    

12. A Layout-Based Rad-Hard DICE Flip-Flop Design

    • Haibin Wang
    • Xixi Dai
    • Li Chen

    OriginalPaper 18 January 2019 Pages: 111 - 117

    

13. Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops

    • Shiva Taghipour
    • Rahebeh Niaraki Asli

    OriginalPaper 02 February 2019 Pages: 119 - 125