1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 14 May 2016 Pages: 241 - 242

2. Test Technology Newsletter

   News 05 May 2016 Pages: 243 - 244

   

3. Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

   • Igor Aleksejev
   • Sergei Devadze
   • Konstantin Shibin

   OriginalPaper 28 April 2016 Pages: 245 - 255

   

4. Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

   • Masahiro Ishida
   • Toru Nakura
   • Kunihiro Asada

   OriginalPaper 02 April 2016 Pages: 257 - 271

   

5. Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

   • Maksim Jenihhin
   • Giovanni Squillero
   • Guilherme Cardoso Medeiros

   OriginalPaper 12 May 2016 Pages: 273 - 289

   

6. A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

   • Mohsen Raji
   • Behnam Ghavami

   OriginalPaper 16 April 2016 Pages: 291 - 305

   

7. Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

   • Hector Villacorta
   • Jaume Segura
   • Victor Champac

   OriginalPaper 10 May 2016 Pages: 307 - 314

   

8. NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

   • T. Copetti
   • G. Cardoso Medeiros
   • F. Vargas

   OriginalPaper 16 May 2016 Pages: 315 - 328

   

9. Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering

   • Sharareh Zamanzadeh
   • Ali Jahanian

   OriginalPaper 28 May 2016 Pages: 329 - 343

   

10. Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network

    • Ehsan Saeedi
    • Md Selim Hossain
    • Yinan Kong

    OriginalPaper 14 May 2016 Pages: 345 - 356

    

11. Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection

    • Abdurrahman A. Nasr
    • Mohamed Z. Abdulmageed

    OriginalPaper 07 April 2016 Pages: 357 - 367

    

12. Real-Time Adaptive Test Algorithm Including Test Escape Estimation Method

    • Christian Streitwieser

    OriginalPaper 25 April 2016 Pages: 369 - 375

    

13. High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications

    • R. Jothin
    • C. Vasanthanayaki

    OriginalPaper 29 April 2016 Pages: 377 - 383

    

14. An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

    • Qingyu Chen
    • Haibin Wang
    • Xuantian Li

    OriginalPaper 29 April 2016 Pages: 385 - 391

    

15. A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

    • Dongdi Zhu
    • Jiongjiong Mo
    • Faxin Yu

    OriginalPaper 23 April 2016 Pages: 393 - 397