Verilog HDL Simulator Technology: A Survey Tze Sin TanBakhtiar Affendi Rosdi OriginalPaper 23 May 2014 Pages: 255 - 269
Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow Pekka MiettinenMikko HonkalaMartti Valtonen OriginalPaper 04 June 2014 Pages: 271 - 285
Learning-oriented Property Decomposition for Automated Generation of Directed Tests Mingsong ChenXiaoke QinPrabhat Mishra OriginalPaper 20 June 2014 Pages: 287 - 306
GPUs Neutron Sensitivity Dependence on Data Type P. RechC. FrostL. Carro OriginalPaper 14 June 2014 Pages: 307 - 316
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test M. de CarvalhoP. BernardiO. Ballan OriginalPaper 27 May 2014 Pages: 317 - 328
Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique Efi ArvanitiYiorgos Tsiatouhas OriginalPaper 22 May 2014 Pages: 329 - 341
A Novel Approach for Analog Circuit Fault Prognostics Based on Improved RVM Chaolong ZhangYigang HeFangming Deng OriginalPaper 25 June 2014 Pages: 343 - 356
Modeling of Physical Defects in PN Junction Based Graphene Devices Sandeep MiryalaMatheus OleiroMassimo Poncino OriginalPaper 15 June 2014 Pages: 357 - 370
Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation Guohua WangQiang LiXiaofeng Meng OriginalPaper 20 May 2014 Pages: 371 - 376
The Effect of Temperature-Induced Quiescent Operating Point Shift on Single-Event Transient Sensitivity in Analog/Mixed-Signal Circuits Yi RenLi Chen OriginalPaper 15 May 2014 Pages: 377 - 382
