1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 111 - 111

2. Test Technology Technical Council Newsletter

   BriefCommunication Pages: 113 - 114

3. Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

   • Bipul C. Paul
   • Kaushik Roy

   OriginalPaper Pages: 115 - 124

4. Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

   • Hafizur Rahaman
   • Debesh K. Das
   • Bhargab B. Bhattacharya

   OriginalPaper Pages: 125 - 142

5. Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2 ^m )

   • Chiou-Yng Lee
   • Che Wun Chiou
   • Jim-Min Lin

   OriginalPaper Pages: 143 - 150

6. Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

   • Yu-Chiun Lin
   • Shi-Yu Huang

   OriginalPaper Pages: 151 - 159

7. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

   • Patrick Girard
   • Olivier Héron
   • Michel Renovell

   OriginalPaper Pages: 161 - 172

8. Crosstalk Induced Fault Analysis and Test in DRAMs

   • Zemo Yang
   • Samiha Mourad

   OriginalPaper Pages: 173 - 187

9. Electro-thermal Stimuli for MEMS Testing in FSBM Technology

   • N. Dumas
   • F. Azaïs
   • P. Nouet

   OriginalPaper Pages: 189 - 198

10. Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems

    • Fei Su
    • Sule Ozev
    • Krishnendu Chakrabarty

    OriginalPaper Pages: 199 - 210