1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 571 - 571

2. List of Reviewers

   OriginalPaper Pages: 573 - 574

3. Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

   • Zainalabedin Navabi
   • Shahrzad Mirkhani
   • Fabrizio Lombardi

   OriginalPaper Pages: 575 - 589

4. Modeling Custom Digital Circuits for Test

   • Soumitra Bose

   OriginalPaper Pages: 591 - 609

5. A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*

   • Michael Goessel
   • Krishnendu Chakrabarty
   • Andreas Leininger

   OriginalPaper Pages: 611 - 622

6. A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

   • Sunil Rafeeque K.P.
   • Vinita Vasudevan

   OriginalPaper Pages: 623 - 638

7. Scan Test Strategy for Asynchronous-Synchronous Interfaces

   • Octavian Petre
   • Hans G. Kerkhoff

   OriginalPaper Pages: 639 - 645

8. Power-Driven Routing-Constrained Scan Chain Design

   • Y. Bonhomme
   • P. Girard
   • S. Pravossoudovitch

   OriginalPaper Pages: 647 - 660

9. Area Minimization of Exclusive-OR Intensive Circuits in FPGAs

   • Seok-Bum Ko

   OriginalPaper Pages: 661 - 665

10. On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression

    • Lei Li
    • Krishnendu Chakrabarty

    OriginalPaper Pages: 667 - 670

11. 2004 Annual Index

    OriginalPaper Pages: 671 - 681