1. Introduction

   • Dominique Borrione

   EditorialNotes Pages: 5 - 5

2. A formalization of a subset of VHDL in the Boyer-Moore logic

   • David M. Russinoff

   OriginalPaper Pages: 7 - 25

3. A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL

   • Peter T. Breuer
   • Luis Sánchez Fernández
   • Carlos Delgado Kloos

   OriginalPaper Pages: 27 - 51

4. Denotational semantics of a synchronous VHDL subset

   • Dominique Borrione
   • Ashraf Salem

   OriginalPaper Pages: 53 - 71

5. A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL

   • Ralf Reetz
   • Thomas Kropf

   OriginalPaper Pages: 73 - 99

6. A Colored Petri Net model of VHDL

   • Serafín Olcoz
   • José Manuel Colom

   OriginalPaper Pages: 101 - 123

7. Translating VHDL into functional symbolic finite-state models

   • Gert Döhmen
   • Ronald Herrmann
   • Hergen Pargmann

   OriginalPaper Pages: 125 - 148