Automatic test pattern generation on multiprocessors: a summary of results

Abstract

Test generation of combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and, for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of a backtrack search algorithm called PODEM, which has been the most successful algorithm for this problem. The sequential PODEM algorithm consumes most of its execution time in generating a test for “hard-to-detect” (HTD) faults and is often unable to detect them even after a large number of bactracks. Our parallel formulation attempts to overcome these limitations by partitioning the search space in order to search it concurrently using multiple processors.

We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. Our results show that parallel search techniques provide good speedups (45–106 on 128 processors) as well as high fault coverage of the HTD faults in reasonable time as compared to the uniprocessor implementation.

Tree search is an integral part of several AI systems. Effective parallel processing of search problems is important in developing high performance knowledge-based systems. Results from this paper show that tree search can be effectively parallelized on large scale parallel processors in the context of practical problems.

This work was partially supported by Army Research Office grant # DAAG29-84-K-0060 to the Artificial Intelligence Laboratory, Office of Naval Research Grant N00014-86-K-0763 to the Computer Science Department, at the University of Texas at Austin.

A large part of this research was performed while the first and second authors were at the University of Texas at Austin.