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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

This chapter introduces a local oscillator (LO) as a building block that finds place in the hearth of every modern wireless transceiver. Initially, we discuss the LO performance metrics such as phase noise, spurious content, frequency granularity, and power consumption in context of down/up conversion in accurate receive and transmit modes. An LO is typically implemented within a phase-locked loop (PLL), a system that has been intensively researched for a number of years. We follow its development from initial, purely analog implementations to modern digitally intensive solutions. We discuss the basic theory of operation with practical implementation in mind. The discussion gradually arrives to recently introduced subsampling PLL architectures that tend to overcome typical performance limitations of prior art, offering extreme low-noise synthesis potential.

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Notes

  1. 1.

    A direct conversion, i.e., zero-Intermediate Frequency (IF) transceiver is depicted in this example.

  2. 2.

    The period of the divider’s output is continuously modulated with accuracy of a single (or several) VCO periods. Δ Σ order determines the number of division factors used, i.e., with how many different VCO periods is the divider’s output period modulated.

  3. 3.

    Note that the loop settles to a condition where Φe is a zero-mean signal, i.e., where ΦREF = ΦDIV.

  4. 4.

    The improvement is somewhat limited since for higher gain G CP, the CP current must increase which also leads to a higher local noise generation of the CP.

  5. 5.

    Valid for small signal approximation of a sinusoid around zero.

  6. 6.

    Maybe the best proof for the potential this system has is in today’s frequency synthesis state of the art. The current record holders in PLL FOM, presented at ISSCC 2018, are two (sub)sampling PLLs [Sharkia18, Sharma18]. Moreover, the subsampling architecture has been successfully and widely applied for high-performance integer-N LO synthesis since its introduction, in digitally intensive configurations [Ru13], ring-oscillator-based [Sogo12] loops, at millimeter frequencies [Szortyka14], and in automotive radar systems [Yi13].

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Authors and Affiliations

  1. IMEC, Leuven, Belgium

    Nereo Markulic, Kuba Raczkowski, Jan Craninckx & Piet Wambacq

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  1. Nereo Markulic
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). Introduction. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_1

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  • DOI: https://doi.org/10.1007/978-3-030-10958-5_1

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