Realization of Junctionless TFET-Based Power Efficient 6T SRAM Memory Cell for Internet of Things Applications

Abstract

The Internet of Things (IoTs) applications have garnered its interest to realize low-power memory circuit based on emerging nanoscale transistors for its data processing unit. Therefore, in this work, we focussed on tunneling mechanism-based tunnel field-effect transistor (TFET) which can be a suitable option beyond-CMOS devices for designing reliable and efficient memory circuits for its key sensing and data processing unit. However, this work is further extended toward low-power design strategy to meet the essential requirements of IoT applications. For this purpose, a junctionless (JL) TFET based on work-function engineering is reported in this work, where a high-k material (HfO$_{2}$) adjacent to the SiO$_{2}$ toward source side is considered underneath the gate region to improve the ON-current of the proposed device. The main benefits of junctionless architecture is that it reduces the fabrication complexity, high thermal budget, and is free from random dopant fluctuations (RDFs). The significant benefits in terms of hold, read, and write static noise margin (SNM) of JLTFET-based six-transistor (6T) memory cell enables its potential application for IoT memory unit.