Abstract
This chapter is related to the paper “System Level Design for Embedded Reconfigurable Systems using MORPHEUS platform” (Brelet et al. (2010) System level design for embedded reconfigurable systems using MORPHEUS platform). It presents a novel approach for designing embedded reconfigurable systems. Reconfigurable systems bring a significant importance for their highly attractive mix of performance density, power efficiency and flexibility. In this chapter, we present a toolset that abstracts the heterogeneity and benefits of a dynamically reconfigurable heterogeneous platform called MORPHEUS (Voros et al. (2009) Dynamic system reconfiguration in heterogeneous platforms, the MORPHEUS approach. This platform consists of a System-on-Chip made of a regular system infrastructure hosting different kinds of heterogeneous reconfigurable engines accelerating some operations. Integrated mechanisms simplify the utilization of these reconfigurable accelerators at design time and minimize the time to fetch and reconfigure a function dynamically at run time. Implementing an application on the platform is made easier and faster by a comprehensive design environment. Industrial use cases from various application domains are also presented and used to evaluate the performance of the platform and assess the MORPHEUS concept.
Partners of the project: Thales Research & Technology (France), Deutsche THOMSON OHG (Germany), INTRACOM Telecom Solutions S.A. (Greece), ALCATEL-LUCENT Deutschland AG (Germany), Thales Optronics SA (France), STMicroelectronics SRL (Italy), PACT XPP Technologies AG (Germany), M2000 (France), Associated Compiler Experts bv (The Netherlands), CriticalBlue (United Kingdom), Universitaet Karlsruhe (Germany), Technische Universiteit Delft (The Netherlands), Commissariat à l’Energie Atomique (France), Université de Bretagne Occidentale (France), Universita di Bologna (Italy), ARTTIC SAS (France), Technische Universitaet Braunschweig (Germany), Technische Universitaet Chemnitz (Germany).
Start–End Date: January 2006-September 2009.
Global Budget/Funding by EU: 16.57 M€/: 8.24 M€.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Brelet P, Grasset A, Bonnot P, Ieromnimon F, Kritharidis D, Voros NS (2010) System level design for embedded reconfigurable systems using MORPHEUS platform. In: Proceedings of the 2010 IEEE annual symposium on VLSI 5 July 2010. ISVLSI. IEEE computer society, Washington, DC, pp 500–505. http://dx.doi.org/10.1109/ISVLSI.2010.13
Voros N, Rosti A, Hübner M (2009) Dynamic system reconfiguration in heterogeneous platforms, the MORPHEUS approach. Springer, Berlin
Mair H, Wang A, Gammie G, Scott D, Royannez P, Gururajarao S, Chau M, Lagerquist R, Ho L, Basude M, Culp N, Sadate A, Wilson D, Dahan F, Song J, Carlson B, Ko U. A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations. Digital Signal Processing, pp 8–9
Clark L, Hoffman E, Miller J, Biyani M, Strazdus S, Morrow M, Velarde K, Yarch M (2001) An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J Solid State Circ 36:1599–1608
Lenormand E, Edelin G (2003) An industrial perspective: pragmatic high-end signal processing environment at Thales. In: Proceedings of the 3rd international workshop on synthesis, architectures, modeling and simulation (SAMOS)
Gast N, Gaujal B (2010) A mean field approach for optimization in discrete time. J Discrete Event Dyn Syst
Klein F, Leao R, Araujo G, Santos L, Azevedo R (2007) A multi-model power estimation engine for accuracy optimization. ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Muhammad R, Apvrille L, Pacalet R (2008) Evaluation of ASIPs design with LISATek: Springer Volume 5114/2008
Clarke P (2002) Chess/checkers tool flow brings verification into play. EETimes article
SystemC Modeling, Synthesis, and Verification in Catapult C, Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oregon, USA. [online] Available: http://www.mentor.com/products/esl/techpubs/
Mitrionics (2008) Low power hybrid computing for efficient software acceleration. White paper
Pellerin D, Thibault EA (2005) Practical FPGA programming in C, Prentice Hall
University of Newcastle upon Tyne (2003) Matlab/Simulink tutorial
Campbell SL, Nikoukhah R (2004) Auxiliary signal design for failure detection. Princeton University Press, Princeton
Bergmann J, McCoy D (2004) Sourcery VSIPL++ HPEC benchmark performance. HPCMP-UGC '06 Proceedings of the HPCMP Users Group Conference
Snir M, Otto S, Huss-Lederman S, Walker D, Dongarra J, MPI the complete reference. [online] Available: http://www.netlib.org/utk/papers/mpi-book/mpi-book.html
Chapman B, Jost G, van der Pas R, Kuck DJ (2008) Using openMP: portable shared memory parallel programming. MIT Press, Cambridge
Fowler M (2008) UML distilled: a brief guide to the standard object modeling language. Published September 25th 2003 by Addison-Wesley Professional
Weilkiens T (2006) Systems engineering with SysML/UML: modeling analysis, design. Hüthing, Heidelberg
PACT XPP Technologies (2005) PACT software design system XPP-IIb (PSDS XPP-IIb)—programming tutorial. Version 3.2, November 2005
Stitt G, Grattan B, Villarreal J, Vahid F (2002) Using on-chip configurable logic to reduce embedded system software energy. IEEE symposium on field-programmable custom computing machines, Napa Valley, USA
Baron M (2004) M2000’s spherical FPGA cores. MicroProcessor report, Dec 2004
Coppola M, Locatelli R, Maruccia G, Pieralisi L, Scandurra A (2004) Spidergon: a novel on-chip communication network. Proceedings of the international symposium on system-on-chip, pp 16–18
Whitty S, Ernst R (2008) A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. In: Proceedings of the IEEE parallel and distributed processing symposium (IPDPS)
Amar A, Boulet P, Dumont P, Projection of the array-OL specification language onto the Kahn process network computation model. [online] Available: http://hal.archives-ouvertes.fr/docs/00/07/04/91/PDF/RR-5515.pdf
CRITICALBLUE (2005) Boosting software processing performance with co-processor synthesis. White paper
Whitty S, Sahlbach H, Hurlburt B, Putzke-Röming W, Ernst R (2010) Application-specific memory performance of a heterogeneous reconfigurable architecture. In: Proceedings of design, automation and test in Europe (DATE)
Acknowledgments
The authors would like to thank all the partners of the project consortium who were involved in studying and providing the required technologies, specifying the requirements and assessing the results. This research was partially funded by the European Community’s 6th Framework Program.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media B.V.
About this paper
Cite this paper
Brelet, P. et al. (2011). Design for Embedded Reconfigurable Systems Using MORPHEUS Platform. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_19
Download citation
DOI: https://doi.org/10.1007/978-94-007-1488-5_19
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-1487-8
Online ISBN: 978-94-007-1488-5
eBook Packages: EngineeringEngineering (R0)