Abstract
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. Furthermore, the implementation of methods that provide robustness are prone to implementation errors. Checks are needed to verify that the nominal behavior of the system did not change due to modifications that are meant to provide robustness. Solutions for both problems are presented in this work.
This work was supported by the Graduate School SyDe, funded by the German Excellence Initiative within the University of Bremen’s institutional strategy.
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Thole, N., Fey, G. (2015). Formal Verification of Robustness. In: Drechsler, R., Kühne, U. (eds) Formal Modeling and Verification of Cyber-Physical Systems. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-09994-7_21
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DOI: https://doi.org/10.1007/978-3-658-09994-7_21
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