Abstract
Image Processing often involves convolutions and Fourier Transforms (DFT and FFT): these specific operations are well implemented by means of a systolic multi-pipeline structure.
Practical implementations require large pipelines, adopting highly integrated circuits that are prone to production defects and run-time faults; efficient fault-tolerance through reconfiguration is then required.
Still, the basic problem of concurrent (or semi-concurrent) testing must be solved prior to any reconfiguration step. Here, we prove how these structures allow to perform testing by a simple technique (based on the classical LSSD method) so that added circuits required due to testing functions is kept very limited.
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References
K.Hwang, F.A.Biggs, Computer architecture for parallel processing, McGraw-Hill, New York (1984)
P.Kogge, The architecture of pipeline computers, McGraw-Hill, New York (1981)
R.Negrini, R.Stefanelli, “Fault-tolerance techniques in array for image processing”, in Pyramidal Systems for Processing and Computer Vision, ed. V.Cantoni, S.Levialdi, pp. 373–392, Springer-Verlag (May 1986)
A.Antola, C.Bonzio, R.Negrini, N.Scarabottolo, G.Storti-Gajani, “SAR Real-Time on-Board Processing: the Architecture”, 2nd Int.I Conf. on Supercomputing, pp. 254–264, Santa Clara (CA)
O.Bruschi, R.Negrini, S.Ravaglia, “Systolic arrays for serial signal processing”, Microprocessing and Microprogramming, vol. 20, n. 1–3, pp. 133–140 (April 1987)
T.E.Mangir, A.Avizienis, “Fault-toleranr design for VLSI: effect of interconnect requirements on yield improvement of VLSI design”, IEEETC, vol. C31, n. 7, pp. 609–615 (July 1982)
T.W.Williams, K.P.Parker, “Design for testability -a survey”, Proc. IEEE, vol. 71, n. 1, pp. 98–112 (Jan. 1983)
A.Antola, “Multiple-transform pipelines for image coding”, Internal Report, Dept. Electronics, Politecnico di Milano, Milano (Sept. 1987)
J.H.McClellan, R.J.Purdy, “Applications of digital signal processing to radar”, in Applications of Digital Signal Processing, ed. A.V.Oppenheim, Prentice-Hall (1978)
R.Negrini, M.G.Sami, R.Stefanelli, “Restructuring and reconfiguring DSP mutli-pipeline arrays”, Proc. MTNS87, Phoenix (June 1987)
M.G.Sami, R.Stefanelli, “Fault-stealing: an approach to fault-tolerance of VLSI processing arrays”, Proc. ICCAS 1985, Beijing (June 1985)
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© 1989 Springer-Verlag Berlin Heidelberg
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Negrini, R., Sami, M.G., Scarabottolo, N., Stefanelli, R. (1989). Fault-Tolerance in Imaging-Oriented Systolic Arrays. In: Eckmiller, R., v.d. Malsburg, C. (eds) Neural Computers. Springer Study Edition, vol 41. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-83740-1_6
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DOI: https://doi.org/10.1007/978-3-642-83740-1_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-50892-2
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