Abstract
Traditionally, the timing of a flipflop is modeled by a single constraint pair of setup and hold times. For timing verification of digital circuits both timing constraints should not be violated. Furthermore, the interdependency of these two quantities is exploited and multiple constraint pairs are taken as valid setup and hold times. STA Tools can be easily constructed by the propagation of arrival times. In this paper, we present a comprehensive study of flipflop timing behavior and extend the timing modeling by explicitly building the functional relationship between clock-to-q delay and timing parameters at flipflop data input in order to break the timing boundaries and thus allow interdependency of different computation stages to be analyzed at gate level. Aging effects HCI and NBTI are also considered in the modeling to pave the way for aging analysis.
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References
The open source liberty library modeling format specification, http://www.opensourceliberty.org/
Lang, A., Bergler, S.: Method and apparatus for circuit verification of meeting setup and hold time requirements (Verfahren und Vorrichtung zum Ueberpruefen einer Schaltung auf Einhaltung von Setup- und Holdzeiten). Patent DE102004044668A1 (2004)
Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Pessimism reduction in static timing analysis using interdependent setup and hold times. In: ISQED 2006, pp. 159–164 (2006)
Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Exploiting setup-hold-time interdependence in static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(6), 1114–1125 (2007)
Srivastava, S., Roychowdhury, J.: Interdependent latch setup/hold time characterization via Euler-Newton curve tracing on state-transition equations. In: DAC 2007, pp. 136–141 (2007)
Srivastava, S., Roychowdhury, J.: Independent and interdependent latch setup/hold time characterization via Newton-Raphson solution and Euler curve tracking of state-transition equations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5), 817–830 (2008)
Sakallah, K.A., Mudge, T.N., Olukotun, O.A.: Analysis and design of latch-controlled synchronous digital circuits. In: DAC 1990, pp. 111–117 (1990)
Gabara, T., Cyr, G., Stroud, C.: Metastability of CMOS master/slave flip-flops. In: CICC 1991, pp. 29.4/1–29.4/6 (1991)
Wu, L., Fang, J., Yan, H., Chen, P., Chen, A.I.-H., Okamoto, Y., Yeh, C.-S., Liu, Z., Iwanishi, N., Yonezawa, N.K.H., Kawakami, Y.: Glacier: A hot carrier gate level circuit characterization and simulation system for vlsi design. In: ISQED 2000, p. 73 (2000)
Kumar, S.V., Kim, C.H., Sapatnekar, S.S.: An analytical model for negative bias temperature instability. In: ICCAD 2006, pp. 493–496 (2006)
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Chen, N., Li, B., Schlichtmann, U. (2011). Timing Modeling of Flipflops Considering Aging Effects. In: Ayala, J.L., GarcÃa-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_7
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DOI: https://doi.org/10.1007/978-3-642-24154-3_7
Publisher Name: Springer, Berlin, Heidelberg
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