Abstract
Scaling supply voltage to sub-threshold region can reach minimum energy consumption but only suits for ultra-low operation frequencies. In order to attain more extensive application, scaling supply voltage to medium-voltage region is an attractive approach especially suiting for mid performances. This paper investigates performances of adiabatic register file in near-threshold and super-threshold regions in terms of energy dissipation and max operating frequency. The adiabatic register file is realized with CPAL (complementary pass-transistor adiabatic logic) circuits. All circuits are simulated with HSPICE at a PTM 45nm CMOS technology by supply voltage varies from 0.4V to 1.0V with 0.1V steps. The simulation results demonstrate that the CPAL register file operating on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions.
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Ni, H., Sheng, X., Hu, J. (2011). Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic. In: Zeng, D. (eds) Future Intelligent Information Systems. Lecture Notes in Electrical Engineering, vol 86. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19706-2_6
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DOI: https://doi.org/10.1007/978-3-642-19706-2_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19705-5
Online ISBN: 978-3-642-19706-2
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