Abstract
Practically all modern video coding standards such as H.264, MPEG-4 and VC-1 are based on hybrid transform based block motion compensated techniques, that employ almost the same coding tools. The same approach is used with numerous non-standard proprietary codecs, with decoders available via Internet as browser plugins. For mobile devices power efficient hardware accelerators have been developed, but usually only a few standards are supported. Consequently, the decoding of the other formats, including the non-standard ones is done by software, sacrificing the battery life. In this paper we present programmable accelerators for arithmetic code decoding and motion compensation, that can be used with multiple video standards. These functions consume more than half of the cycles in software based decoders. Although the accelerators were originally designed for H.264 standard, they are rather generic for the respective coding tools. They have been implemented on application specific processor technology for flexibility and energy efficiency with the aim of achieving the performance needed for decoding high definition (1920x1088, 30 fps) video.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
ISO/IEC 14496-2:2004: Information technology - Coding of audio-visual objects - Part 2: Visual. ISO/IEC. Third edn. (June 2004)
ISO/IEC 14496-10:2005; Recommendation ITU-T H.264: SERIES H: AUDIOVISUAL AND MULTIMEDIA SYSTEMS Infrastructure of audiovisual services - Coding of moving: Advanced video coding for generic audiovisual services video. ITU-T (November 2005)
Fitzek, F.H.P., Reichert, F.: Mobile Phone Programming: and its Application to Wireless Networking. Springer, Heidelberg (2007)
SMPTE 421M-2006: VC-1 Compressed Video Bitstream Format and Decoding Process. SMPTE (February 2006)
Jer-Min, H., Chun-Jen, T.: Analysis of an soc architecture for mpeg reconfigurable video coding framework. In: IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 27-30, pp. 761–764 (2007)
Eeckhaut, H., Christiaens, M., Stroobandt, D., Nollet, V.: Optimizing the critical loop in the h.264/avc cabac decoder. In: IEEE International Conference on Field Programmable Technology, FPT 2006, December 2006, pp. 113–118 (2006)
Jääskeläinen, P., Guzma, V., Cilio, A., Pitkänen, T., Takala, J.: Codesign toolset for application-specific instruction-set processors, vol. 6507. SPIE (2007) 65070X
On2 Technologies (2008), http://www.on2.com
ISO/IEC JTC1/SC29/WG11 N8069: Reconfigurable Video Coding Requirements v.2.0. ISO/IEC (November 2006)
Richardson, I., Bystrom, M., Kannangara, S., Frutos, D.: Dynamic configuration: Beyond video coding standards. In: IEEE System on Chip Conference. IEEE, Los Alamitos (2008)
Lucarz, C., Mattavelli, M., Thomas-Kerr, J., Janneck, J.: Reconfigurable media coding: A new specification model for multimedia coders. In: IEEE Workshop on Signal Processing Systems, October 2007, pp. 481–486 (2007)
Wang, S.Z., Lin, T.A., Liu, T.M., Lee, C.Y.: A new motion compensation design for h.264/avc decoder. In: IEEE International Symposium on Circuits and Systems, ISCAS 2005, May 2005, vol. 5, pp. 4558–4561 (2005)
Tsai, C.Y., Chen, T.C., Chen, T.W., Chen, L.G.: Bandwidth optimized motion compensation hardware design for h.264/avc hdtv decoder. In: 48th Midwest Symposium on Circuits and Systems, August 2005, vol. 2, pp. 1199–1202 (2005)
Zatt, B., Ferreira, V., Agostini, L.V., Wagner, F.R., Susin, A.A., Bampi, S.: Motion compensation hardware accelerator architecture for h.264/avc. In: Mery, D., Rueda, L. (eds.) PSIVT 2007. LNCS, vol. 4872, pp. 24–35. Springer, Heidelberg (2007)
Li, Y., He, Y.: Bandwidth optimized and high performance interpolation architecture in motion compensation for h.264/avc hdtv decoder. J. Signal Process. Syst. 52(2), 111–126 (2008)
Marpe, D., Schwarz, H., Wiegand, T.: Context-based adaptive binary arithmetic coding in the h.264/avc video compression standard. IEEE Transactions on Circuits and Systems for Video Technology 13(7), 620–636 (2003)
On2 Technologies (2008), http://www.on2.com
ARM (2008), http://www.arm.com/products/cpus/arm926ej-s.html
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 IFIP International Federation for Information Processing
About this paper
Cite this paper
Rintaluoma, T., Reinikka, T., Rouvinen, J., Boutellier, J., Jääskeläinen, P., Silvén, O. (2009). Programmable Accelerators for Reconfigurable Video Decoder. In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_5
Download citation
DOI: https://doi.org/10.1007/978-3-642-03138-0_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03137-3
Online ISBN: 978-3-642-03138-0
eBook Packages: Computer ScienceComputer Science (R0)