Abstract
Parallel multipliers can be optimized using the intrinsic arithmetic equivalencies in their reduction-tree. In this paper, we propose a method to reduce the dynamic power consumption in parallel multipliers, operating within systems with effective word-length variation. Word-length variation induces a certain pattern of spatiotemporal correlations. The proposed method is capable to take such correlations into account resulting better solutions. The experimental results show about 16-21% reduction in the average number of transitions compared to random parallel multipliers.
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Oskuii, S.T., Kjeldsberg, P.G., Lundheim, L., Havashki, A. (2009). Power Optimization of Parallel Multipliers in Systems with Variable Word-Length. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_11
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DOI: https://doi.org/10.1007/978-3-540-95948-9_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
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