Abstract
A hardware Trojan can be inserted in a gate-level netlist by a rogue designer, or it already exists in a provided gate-level netlist (e.g., a firm intellectual property) by an untrusted third-party design developer. Various techniques have been proposed to prevent hardware Trojan insertion or to detect hardware Trojans at the gate level. This chapter studies some of the major existing techniques and discusses their effectiveness.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
B. Çakir, S. Malik, Hardware Trojan detection for gate-level ICs using signal correlation based clustering, in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2015), pp. 471–476
S.K. Haider, C. Jin, M. Ahmad, D.M. Shila, O. Khan, M.V. Dijk, HaTCh: a formal framework of hardware Trojan design and detection, Cryptology ePrint Archive, Report 2014/943 (2014)
W. Hu, D. Mu, J. Oberg, B. Mao, M. Tiwari, T. Sherwood, R. Kastner, Gate-level information flow tracking for security lattices. ACM Trans. Des. Autom. Electron. Syst. 20(1), 2:1–2:25 (2014)
M. Oya, Y. Shi, M. Yanagisawa, N. Togawa, A score-based classification method for identifying hardware-Trojans at gate-level netlists, in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2015), pp. 465–470
H. Salmani, COTD: reference-free hardware trojan detection and recovery based on controllability and observability in gate-level netlist. IEEE Trans. Inf. Forensics Secur. 12(2), 338–350 (2017)
G.A.F. Seber, Multivariate Observations (Wiley, Hoboken, 1984)
Synopsys’s TetraMAX. http://www.synopsys.com/Tools/Pages/default.aspx
Trust-HUB benchmarks. https://www.trust-hub.org/taxonomy
A. Waksman, M. Suozzo, S. Sethumadhavan, FANCI: identification of stealthy malicious logic using Boolean functional analysis, in Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security (CCS) (2013), pp. 697–708
C. Wu, L. Wang, X. Wen, VLSI Test Principles and Architectures: Design for Testability. The Morgan Kaufmann Series in Systems on Silicon (Morgan Kaufmann Publishers, San Francisco, 2006)
J. Zhang, F. Yuan, Q. Xu, DeTrust: defeating hardware trust verification with stealthy implicitly-triggered hardware Trojans,in Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security (CCS) (2014), pp. 153–166
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this chapter
Cite this chapter
Salmani, H. (2018). Design Techniques for Hardware Trojans Prevention and Detection at the Gate Level. In: Trusted Digital Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-79081-7_5
Download citation
DOI: https://doi.org/10.1007/978-3-319-79081-7_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-79080-0
Online ISBN: 978-3-319-79081-7
eBook Packages: EngineeringEngineering (R0)