Abstract
SRAM-based FPGAsare more vulnerable to single-event, particularly the single-event upset (SEU). Triple modular redundancy (TMR) protection method is a good method to prevent the FPGA system from being destroyed. At the same time, the area cost of an FPGA project plays an important role in designing an FPGA system. What’s more, the protection method can enlarge the area cost, it may exceed the maximum of the FPGAs. So we should know the changes of area when the project is protected. This article firstly discusses a new way to estimate the area of an FPGA project, which is based on its used resources, such as Look-Up-Table (LUT), Brams, IO and so on. Then, we offer the model to estimate the new area cost of the project when it’s protected by TMR. At last, we apply TMR Tool to verify the models and the results are sound.
This work was supported by the National Natural Science Foundation of China under Grants No. 61571346 and No. 61305041.
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References
Legat, U., Biasizzo, A., Novak, F.: SEU recovery mechanism for SRAM-based FPGAs. IEEE Trans. Nucl. Sci. 59(5), 2562–2571(2012)
Bidokhti, N.: SEU concept to reality (allocation, prediction, mitigation). In: Reliability & Maintainability Symposium, pp. 1–5. IEEE (2010)
Single-Event Upset Mitigation for Xilinx FPGA Block Memories. http://www.xilinx.com/support/documentation/application_notes/xapp962.pdf
Samudrala, P.K., Ramos, J., Katkoori, S.: Selective triple modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs. IEEE Trans. Nucl. Sci. 51(5), 2957–2969(2014)
Matsumoto, K., Uehara, M., Mori, H.: Stateful TMR for transient faults, world automation congress (WAC), pp. 1–6. IEEE (2010)
Lam, S.K., Srikanthan, T.: Estimating area costs of custom instructions for FPGA-based Reconfigurable Processors. J. 89–94 (2007)
XinlinxVirtex-4SeriesFPGAs. http://china.xilinx.com/publications/matrix/virtex4_color.pdf
Virtex-4 FPGA Configuration User Guide, Xilinx Inc.UG071, ver. 1.10 (2008)
Quinn, H., Morgan, K., Graham, P., et al.: Domain crossing errors: limitations on single device triple-modular redundancy circuits in xilinx FPGAs. IEEE Trans. Nucl. Sci. 54(6), 2037–2043 (2008)
Xilinx TRMTool User Guide: TMRTool Software Version 9.2i, Xilinx Inc, UG156, ver. 2.2 (2009)
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He, H., Guo, B., Yan, Y. (2017). Area Estimation for Triple Modular Redundancy Field Programmable Gate Arrays. In: Pan, JS., Snášel, V., Sung, TW., Wang, X. (eds) Intelligent Data Analysis and Applications. ECC 2016. Advances in Intelligent Systems and Computing, vol 535. Springer, Cham. https://doi.org/10.1007/978-3-319-48499-0_30
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DOI: https://doi.org/10.1007/978-3-319-48499-0_30
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