An Efficient Bridge Architecture for NoC Based Systems on FPGA Platform

Abstract

The growing demands at the electronic consumer application areas have lent the requirement of embedded devices to be integrated on the same System on Chip (SoC). The SoC uses on-chip bus interconnection with shared memory communication. However, these buses are not scalable and limited to specific interface protocol. The Network on chip (NoC) provides a better interconnection solution for the SoC with reliable and scalable features. The bridge architecture is necessary to communicate the SoC through the NoC paradigm. Thus, the manuscript introduces an efficient bridge with Ethernet-Media Access Control (MAC) and also presented an interconnection of the bridge architecture having NoC based systems on targeted FPGA. The bridge architecture is consists of FIFO buffers, Serializer, priority based Arbiter, Credit counter Packet formation for Ethernet-MAC Transceiver module followed by packet parser and deserializer. The bridge with a single router and 2X2 NoC based systems are designed by using congestion free adaptive XY-routing. The proposed bridge architecture and the bridge with NoC are implemented over Artix-7 FPGA with prototyping. The performance analysis is considered in terms of Average latency, Maximum throughput at different packet injection rate for a bridge with NoC based systems.