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Trojan Detection Using Dynamic Current Analysis

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System-on-Chip Security

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Abstract

Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this chapter, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of multiple excitation of rare switching (MERS) that can significantly increase Trojan detection sensitivity. (1) It presents in detail a scalable statistical test generation method, which can generate high-quality testset for creating high relative activity in arbitrary Trojan instances; (2) it analyzes the effectiveness of generated testset in terms of Trojan coverage; and (3) it describes two judicious reordering methods that can further tune the testset and greatly improve the side-channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using side-channel analysis.

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Notes

  1. 1.

    We have performed structural partitioning [15] with partition factor p = 50%, which generally achieves better SCS than a skewed partition. If the designer can afford the cost, different partition factor p can be explored.

References

  1. M. Banga, M. Hsiao, A region based approach for the identification of hardware Trojans, in IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) (2008)

    Google Scholar 

  2. M. Banga, M. Chandrasekar, L. Fang, M. Hsiao, Guided test generation for isolation and detection of embedded Trojans in ICs, in ACM Great Lakes Symposium on VLSI (GLSVLSI) (2008), pp. 363–366

    Google Scholar 

  3. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, Parameter variations and impact on circuits and microarchitecture, in ACM/IEEE Design Automation Conference (DAC) (2003), pp. 338–342

    Google Scholar 

  4. R. Chakraborty, S. Bhunia, Security against hardware Trojan through a novel application of design obfuscation, in ACM International Conference on Computer-Aided Design (ICCAD) (2009), pp. 113–116

    Google Scholar 

  5. R. Chakraborty, F. Wolff, S. Paul, C. Papachristou, S. Bhunia, MERO: a statistical approach for hardware Trojan detection, in International Workshop on Cryptographic Hardware and Embedded Systems (2009), pp. 396–410

    Google Scholar 

  6. J. Cruz, Y. Huang, P. Mishra, S. Bhunia, An automated configurable Trojan insertion framework for dynamic trust benchmarks, in Design Automation and Test in Europe (DATE), Dresden, Germany, March 19–23 (2018)

    Google Scholar 

  7. J. Cruz, P. Mishra, S.Bhunia, The metric matters: how to measure trust, in Design Automation Conference (DAC), Las Vegas, June 2–6 (2019)

    Book  Google Scholar 

  8. D. Du, S. Narasimhan, R. Chakraborty, S. Bhunia, Self-referencing: a scalable side-channel approach for hardware Trojan detection, in International Workshop on Cryptographic Hardware and Embedded Systems (CHES) (2010), pp. 173–187

    Chapter  Google Scholar 

  9. S. Dupuis, P. Ba, G. Natale, M. Flottes, B. Rouzeyre, A novel hardware logic encryption technique for thwarting illegal overproduction and hardware Trojans, in IEEE 20th International On-Line Testing Symposium (IOLTS) (2014), pp. 49–54

    Google Scholar 

  10. F. Farahmandi, Y. Huang, P. Mishra, Trojan localization using symbolic algebra, in Asia and South Pacific Design Automation Conference (ASPDAC) (2017), pp. 591–597

    Google Scholar 

  11. Y. Huang, P. Mishra, Trace buffer attack on the AES cipher. J. Hardw. Syst. Secur. 1(1), 68–84 (2017)

    Article  Google Scholar 

  12. Y. Huang, S. Bhunia, P. Mishra, MERS: statistical test generation for side-channel analysis based Trojan detection, in ACM Conference on Computer and Communications Security (CCS) (2016), pp. 130–141

    Google Scholar 

  13. Y. Huang, S. Bhunia, P. Mishra, Scalable test generation for Trojan detection using side channel analysis. IEEE Trans. Inf. Forensics Secur. 13(11), 2746–2760 (2018)

    Article  Google Scholar 

  14. Y. Jin, Y. Makris, Hardware Trojan detection using path delay fingerprint, in IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) (2008)

    Google Scholar 

  15. G. Karypis, R. Aggarwal, V. Kumar, S. Shekhar, Multilevel hypergraph partitioning: applications in VLSI domain. IEEE Trans. Very Large Scale Integr. Syst. 7(1), 69–79 (1999)

    Article  Google Scholar 

  16. Y. Lyu, P. Mishra, A survey of side channel attacks on caches and countermeasures. J. Hardw. Syst. Secur. 2, 33–50 (2018)

    Article  Google Scholar 

  17. Y. Lyu, P. Mishra, Efficient test generation for Trojan detection using side channel analysis, in Design Automation and Test in Europe (DATE), Florence, Italy, March 25–29 (2019)

    Google Scholar 

  18. P. Mishra, S. Bhunia, M. Tehranipoor (eds.) Hardware IP Security and Trust. Springer, Basel (2017). ISBN 9783319490250

    Google Scholar 

  19. OpenCores, Project aes_core and dlx. http://www.opencores.org

  20. I. Park, E.J. McCluskey, Launch-on-shift-capture transition tests, in IEEE International Test Conference, Santa Clara, CA (2008), pp. 1–9

    Google Scholar 

  21. I. Pomeranz, S. Reddy, A measure of quality for n-detection test sets. IEEE Trans. Comput. 53(11), 1497–1503 (2004)

    Article  Google Scholar 

  22. R. Rad, J. Plusquellic, M. Tehranipoor, A sensitivity analysis of power signal methods for detecting hardware Trojans under real process and environmental conditions. IEEE Trans. Very Large Scale Integr. Syst. 18(12), 1735–1744 (2010)

    Article  Google Scholar 

  23. J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Security analysis of logic obfuscation, in ACM/IEEE Design Automation Conference (DAC) (2012), pp. 83–89

    Google Scholar 

  24. S. Saha, R. Chakraborty, S. Nuthakki, Anshul, D. Mukhopadhyay, Improved test pattern generation for hardware Trojan detection using genetic algorithm and boolean satisfiability, in International Workshop on Cryptographic Hardware and Embedded Systems (2015), pp. 577–596

    Google Scholar 

  25. H. Salmani, M. Tehranipoor, Layout-aware switching activity localization to enhance hardware Trojan detection. IEEE Trans. Inf. Forensics Secur. 7(1), 76–87 (2012)

    Article  Google Scholar 

  26. H. Salmani, M. Tehranipoor, J. Plusquellic, A novel technique for improving hardware Trojan detection and reducing Trojan activation time. IEEE Trans. Very Large Scale Integr. Syst. 20(1), 112–125 (2012)

    Article  Google Scholar 

  27. P. Subramanyan, S. Ray, S. Malik, Evaluating the security of logic encryption algorithms, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2015), pp. 137–143

    Google Scholar 

  28. A.K. Suhag, V. Shrivastava, Delay testable enhanced scan flip-flop: DFT for high fault coverage, in International Symposium on Electronic System Design, Kochi, Kerala (2011), pp. 129–133

    Google Scholar 

  29. S. Wei, M. Potkonjak, Scalable hardware Trojan diagnosis. IEEE Trans. Very Large Scale Integr. Syst. 20(6), 1049–1057 (2012)

    Article  Google Scholar 

  30. F. Wolff, C. Papachristou, S. Bhunia, R.S. Chakraborty, Towards Trojan-free trusted ICs: problem analysis and detection scheme, in Design, Automation and Test in Europe (DATE) (2008), pp. 1362–1365

    Google Scholar 

  31. G. Xu, A.D. Singh, Low cost launch-on-shift delay test with slow scan enable, in IEEE European Test Symposium (ETS’06), Southampton (2006), pp. 9–14

    Google Scholar 

  32. B. Zhou, W. Zhang, S. Thambipillai, J. Teo, A low cost acceleration method for hardware Trojan detection based on fan-out cone analysis, in ACM International Conference on Hardware Software Codesign and System Synthesis (2014), p. 28

    Google Scholar 

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Authors and Affiliations

  1. University of Florida, Gainesville, FL, USA

    Farimah Farahmandi & Prabhat Mishra

  2. Google, Mountain View, CA, USA

    Yuanwen Huang

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  1. Farimah Farahmandi
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Farahmandi, F., Huang, Y., Mishra, P. (2020). Trojan Detection Using Dynamic Current Analysis. In: System-on-Chip Security. Springer, Cham. https://doi.org/10.1007/978-3-030-30596-3_10

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  • DOI: https://doi.org/10.1007/978-3-030-30596-3_10

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-30595-6

  • Online ISBN: 978-3-030-30596-3

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