Abstract
This work describes the implementation and operation features for a Phase-Locked Loop (PLL) architecture-based frequency synthesizer for clock generation and digital systems driving. From a programmable structure, considering an input reference frequency FREF = 50 MHz, schematic level simulation results indicate the possibility for generation of 3 distinct output frequencies, according to the transient response limits: TP (peak time) = 1.9 µs, TS (settling time) = 2 µs, and MP (maximum overshoot) <8%. The system was implemented through Cadence Virtuoso Analog Environment (ADE) from UMC CMOS technology (0.18 um), considering power supply VDD = 1.8 V.
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Raphael, R.N.S., Pinto Jr., A.M., Manera, L.T., Finco, S. (2019). Phase-Locked Loop (PLL)-Based Frequency Synthesizer for Digital Systems Driving. In: Iano, Y., Arthur, R., Saotome, O., Vieira Estrela, V., Loschi, H. (eds) Proceedings of the 4th Brazilian Technology Symposium (BTSym'18). BTSym 2018. Smart Innovation, Systems and Technologies, vol 140. Springer, Cham. https://doi.org/10.1007/978-3-030-16053-1_38
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DOI: https://doi.org/10.1007/978-3-030-16053-1_38
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