Abstract
Field programmable gate arrays (FPGAs) are examples of complex programmable system-on-chip (PSoC) platforms and comprise dedicated DSP hardware resources and distributed memory. They are ideal platforms for implementing computationally complex DSP systems for image processing and radar, sonar and signal processing. The chapter describes how decidable signal processing graphs are mapped onto such platforms and shows how parallelism and pipelining can be controlled to achieve the required speed using minimal hardware resource. The work shows how the techniques outlined there are used to build efficient FPGA implementations. The process is demonstrated for a number of DSP circuits including a finite impulse response (FIR) filter, lattice filter and a more complex adaptive signal processing design, namely a least means squares (LMS) filter.
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Acknowledgements
The author would like to acknowledge the effort and help of colleagues Dr Ying Yi and Dr Stephen McKeown in generating the results for the adaptive LMS and FIR filter examples respectively. Acknowledgement is also given to the numerous researchers who worked on this topic over the years, Dr Tim Courtney, Dr Richard Turner, Dr John McAllister and Dr Lok Kee Ting.
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Woods, R. (2013). Mapping Decidable Signal Processing Graphs into FPGA Implementations. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_42
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DOI: https://doi.org/10.1007/978-1-4614-6859-2_42
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