Skip to main content

DSP Systems Using Three-Dimensional Integration Technology

  • Chapter
  • First Online:
Handbook of Signal Processing Systems
  • 5999 Accesses

Abstract

As three-dimensional (3D) integration technology becomes mature and starts to enter mainstream markets, it has attracted exploding interest from integrated circuit and system research community. This chapter discusses and demonstrates the exciting opportunities and potentials for digital signal processing (DSP) circuit and system designers to exploit 3D integration technology. In particular, this chapter advocates a 3D logic-DRAM integration design paradigm and discusses the use of 3D logic-memory integration in both programmable digital signal processors and application-specific digital signal processing circuits. To further demonstrate the potential, this chapter presents case studies on applying 3D logic-DRAM integration to clustered VLIW (very long instruction word) digital signal processors and application-specific video encoders. Since DSP systems using 3D integration technology is still in its research infancy, by presenting some first discussions and results, this chapter aims to motivate greater future efforts from DSP system research community to explore this new and rewarding research area.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 219.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 279.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Ababei, C., Feng, Y., Goplen, B., Mogal, H., Zhang, T., Bazargan, K., Sapatnekar, S.: Placement and routing in 3D integrated circuits. IEEE Design & Test of Computers 22, 520–531 (2005)

    Article  Google Scholar 

  2. Abraham, S.G., Mahlke, S.A.: Automatic and efficient evaluation of memory hierarchies for embedded systems. In: 32nd Annual International Symposium on Microarchitecture(MICRO-32), pp. 114–125 (1999)

    Google Scholar 

  3. Banerjee, K., Souri, S., Kapur, P., Saraswat, K.: 3-d ics: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE 89, 602–633 (2001)

    Article  Google Scholar 

  4. Barth, J., Reohr, W., Parries, P., Fredeman, G., Golz, J., Schuster, S., Matick, R., Hunter, H., Tanner, C., Harig, J., Hoki, K., Khan, B., Griesemer, J., Havreluk, R., Yanagisawa, K., Kirihata, T., Iyer, S.: A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier. IEEE Journal of Solid-State Circuits 43, 86–95 (2008)

    Article  Google Scholar 

  5. Bernstein, K., Andry, P., Cann, J., Emma, P., Greenberg, D., Haensch, W., Ignatowski, M., Koester, S., Magerlein, J., Puri, R., Young, A.: Interconnects in the third dimension: Design challenges for 3D ICs. In: Proc. of ACM/IEEE Design Automation Conference (DAC), pp. 562–567 (2007)

    Google Scholar 

  6. Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G., Reinhardt, S.K.: The m5 simulator: Modeling networked systems. IEEE Micro 26, 2006 (2006)

    Article  Google Scholar 

  7. Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H.: Die Stacking (3D) Microarchitecture. In: Proc. of IEEE/ACM International Symposium on Microarchitecture (Micro), pp. 469–479 (2006)

    Google Scholar 

  8. Burns, J., Aull, B., Chen, C., Chen, C., Keast, C., Knecht, J., Suntharalingam, V., Warner, K., Wyatt, P., Yost, D.: A Wafer-Scale 3-D Circuit Integration Technology. IEEE Trans. Electron Devices 53, 2507–2516 (2006)

    Article  Google Scholar 

  9. CACTI: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. http://www.hpl.hp.com/research/cacti/

  10. Chakrapani, L.N., Gyllenhaal, J., Hwu, W.W., Mahlke, S.A., Palem, K.V., Rabbah, R.M.: Trimaran: An infrastructure for research. In: in Instruction-Level Parallelism. Lecture Notes in Computer Science, p. 2005 (2004)

    Google Scholar 

  11. Chau, L.P., Jing, X.: Efficient three-step search algorithm for block motion estimation video coding. In: Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 421–424 (2003)

    Google Scholar 

  12. Chen, K.N., Lee, S., Andry, P., Tsang, C., Topol, A., Lin, Y., Lu, J., Young, A., Ieong, M., Haensch, W.: Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits. In: Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 367–370 (2006)

    Google Scholar 

  13. Chen, M., Chen, E., Lai, J.Y., Wang, Y.P.: Thermal Investigation for Multiple Chips 3D Packages. In: Proc. of Electronics Packaging Technology Conference, pp. 559–564 (2008)

    Google Scholar 

  14. Claasen, T.: An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology. Proceedings of the IEEE 94, 1121–1137 (2006)

    Article  Google Scholar 

  15. Cong, J.: An interconnect-centric design flow for nanometer technologies. Proceedings of the IEEE 89, 505–528 (2001)

    Article  Google Scholar 

  16. Cong, J., Luo, G.: A multilevel analytical placement for 3D ICs. In: Proc. of Asia and South Pacific Design Automation Conference, pp. 361–366 (2009)

    Google Scholar 

  17. Cong, J., Zhang, Y.: Thermal Via Planning for 3-D ICs. In: Proc. of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 745–752 (2005)

    Google Scholar 

  18. Crowley, M., Al-Shamma, A., Bosch, D., Farmwald, M., Fasoli, L.: 512 Mb PROM with 8 layers of antifuse/diode cells. In: IEEE Intl. Solid-State Circuit Conf. (ISSCC), p. 284 (2003)

    Google Scholar 

  19. Emma, P., Kursun, E.: Is 3D chip technology the next growth engine for performance improvement? IBM Journal of Research and Development 32(6), 541–552 (2008)

    Article  Google Scholar 

  20. Fisher, J.A., Faraboschi, P., Young, C.: Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Morgan Kaufmann (2004)

    Google Scholar 

  21. Garrou, P., Bower, C., Ramm, P.: Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits. Wiley (2008)

    Google Scholar 

  22. Gibert, E., Sanchez, J., Gonzales, A.: Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor. In: Proceedings of the 35 th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 123–133 (2002)

    Google Scholar 

  23. Gibert, E., Sanchez, J., Gonzales, A.: Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. In: Proceedings of the International Symposium on Code Generation and Optimization, pp. 193–203 (2003)

    Google Scholar 

  24. Goplen, B., Sapatnekar, S.: Placement of thermal vias in 3-D ICs using various thermal objectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 692–709 (2006)

    Article  Google Scholar 

  25. Gu, S., Marchal, P., Facchini, M., Wang, F., Suh, M., Lisk, D., Nowak, M.: Stackable memory of 3D chip integration for mobile applications. In: Proc. of IEEE International Electron Devices Meeting (IEDM), pp. 1–4 (2008)

    Google Scholar 

  26. Harrer, H., Katopis, G., Becker, W.: From chips to systems via packaging - A comparison of IBM’s mainframe servers. IEEE Circuits and Systems Magazine 6, 32–41 (2006)

    Article  Google Scholar 

  27. He, Z.L., Tsui, C.Y., Chan, K.K., Liou, M.: Low-power vlsi design for motion estimation using adaptive pixel truncation. IEEE Trans. on Circuits and Systems for Video Technology 10(5), 669–678 (2000)

    Article  Google Scholar 

  28. Healy, M., Vittes, M., Ekpanyapong, M., Ballapuram, C.S., Lim, S.K., Lee, H.H.S., Loh, G.H.: Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 38–52 (2007)

    Article  Google Scholar 

  29. Ho, R., Mai, K.W., Horowitz, M.A.: The future of wires. Proceedings of the IEEE 89, 490–504 (2001)

    Article  Google Scholar 

  30. Horowitz, M., Stark, D., Alon, E.: Digital circuit design trends. IEEE Journal of Solid-State Circuits 43, 757–761 (2008)

    Article  Google Scholar 

  31. Huang, W., Allen-Ware, M., Carter, J., Cheng, E., Skadron, K., Stan, M.: Temperature-aware architecture: Lessons and opportunities. IEEE Micro 31(3), 82–86 (2011)

    Article  Google Scholar 

  32. Huang, Y., Chen, T.C., Tsai, C.H., Chen, C.Y., Chen, T.W., Chen, C.S., Shen, C.F., Ma, S.Y., Wang, T.C., Hsieh, B.Y., Fang, H.C., Chen, L.G.: A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications. In: International Solid-State Circuit Conference, pp. 128–129. San Francisco (2005)

    Google Scholar 

  33. Hwang, C.G.: New paradigms in the silicon industry. In: Proc. of Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 19–26 (2006)

    Google Scholar 

  34. International Technology Roadmap for Semiconductors(ITRS): http://www.itrs.net

  35. Itoh, K.: VLSI Memory Chip Design. Springer (2001)

    Google Scholar 

  36. Jain, A., Jones, R., Chatterjee, R., Pozder, S.: Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits. IEEE Transactions on Components and Packaging Technologies 33(1), 56–63 (2010)

    Article  Google Scholar 

  37. Jaspers, E., de With, P.: Bandwidth reduction for video processing in consumer systems. IEEE Trans. on Consumer Electronics 47(4), 885–894 (2001)

    Article  Google Scholar 

  38. Jung, S.M., Jang, J., Cho, W., Moon, J., Kwak, K.: The Revolutionary and Truly 3-Dimensional 25F2 SRAM Technology with the Smallest S3 (Stacked Single-Crystal Si) cell, 0.16μm2, and SSTFT (Stacked Single-Crystal Thin Film Transistor) for Ultra High Density SRAM. In: Proc. of Symposium on VLSI Technology, pp. 228–229 (2004)

    Google Scholar 

  39. Jung, S.M., Jang, J., Kim, K.: Three Dimensionally Stacked NAND Flash Memory Technology Using Stacked Single Crystal Si Layers in ILD and TANOS Structure for Beyond 30 nm Node. In: Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 37–40 (2006)

    Google Scholar 

  40. Kathail, V., Schlansker, M.S., Rau, B.R.: Hpl-pd architecture specification: Version 1.1. Tech. rep., Hewlett-Packard Company (2000)

    Google Scholar 

  41. Kgil, T., D’Souza, S., Saidi, A., Binkert, N., Dreslinski, R., Reinhardt, S., Flautner, K., Mudge, T.: PicoServer: Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor. In: Proc. of 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2006)

    Google Scholar 

  42. Khailany, K., Williams, T., Lin, J., Long, E.P., Rygh, M., W.Tovey, D., J.Dally, W.: A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. IEEE JOURNAL OF SOLID-STATE CIRCUITS 43 (2008)

    Google Scholar 

  43. Kim, M., Hwang, I., Chae, S.I.: A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. In: Proc. Asia and South Pacific Design Automation Conference, pp. 631–634 (2005)

    Google Scholar 

  44. Koester, S.J., Young, A.M., Yu, R.R., Purushothaman, S., Chen, K.N., La Tulipe, D.C., Rana, N., Shi, L., Wordeman, M.R., Sprogis, E.J.: Wafer-level 3D integration technology. IBM Journal of Research and Development 52(6), 583–597 (2008)

    Article  Google Scholar 

  45. Lapsley, P., Bier, J., Shoham, A., Lee, E.A.: DSP Processor Fundamentals: Architectures and Features. IEEE Press (1997)

    MATH  Google Scholar 

  46. Lee, C., Potkonjak, M., Mangione-Smith, W.: MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In: Proc. of IEEE/ACM International Symposium on Microarchitecture, pp. 330–335 (1997)

    Google Scholar 

  47. Lee, S., Chen, K.N., Lu, J.Q.: Wafer-to-wafer alignment for three-dimensional integration: A review. Journal of Microelectromechanical Systems 20(4), 885–898 (2011)

    Article  Google Scholar 

  48. Li, R., Zeng, B., Liou, M.L.: A new three-step search algorithm for block motion estimation. IEEE Trans. on Circuits and Systems for Video Technology 4, 438–442 (Aug.)

    Google Scholar 

  49. Liu, C.C., Ganusov, I., Burtscher, M., Tiwari, S.: Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design and Test of Computers 22, 556?64 (2005)

    Google Scholar 

  50. Loh, G.: 3D-stacked memory architecture for multi-core processors. In: Proceedings of the 35th ACM/IEEE Intl. Conf. on Computer Architecture (2008)

    Google Scholar 

  51. Loh, G., Xie, Y., Black, B.: Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27, 31–48 (2007)

    Article  Google Scholar 

  52. Lu, J.Q.: 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems. Proceedings of the IEEE 97, 18–30 (2009)

    Article  Google Scholar 

  53. Lu, J.Q., Cale, T., Gutmann, R.: Wafer-level three-dimensional hyper-integration technology using dielectric adhesive wafer bonding. Materials for Information Technology: Devices, Interconnects and Packaging (Eds. E. Zschech, C. Whelan, T. Mikolajick) pp. 386–397 (Springer-Verlag (London) Ltd, August 2005)

    Google Scholar 

  54. Matick, R., Schuster, S.: Logic-based eDRAM: Origins and rationale for use. IBM J. Res. & Dev. 49, 145–165 (2005)

    Article  Google Scholar 

  55. M.Facchini, T.Carlson, A.Vignon, M.Palkovic, F.Catthoor, W.Dehaene, L.Benini, P.Marchal: System-level power/performance evaluation of 3d stacked drams for mobile applications. In: Proc. of Design, Automation & Test in Europe Conference & Exhibition, pp. 923–928 (2009)

    Google Scholar 

  56. Moor, P.D., Ruythooren, W., Soussan, P., Swinnen, B., Baert, K., Hoof, C.V., Beyne, E.: Recent advances in 3d integration at imec. Enabling Technologies for 3-D Integration (edited by C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)

    Google Scholar 

  57. Morrow, P., Black, B., Kobrinsky, M., Muthukumar, S., Nelson, D., Park, C.M., Webb, C.: Design and fabrication of 3d microprocessors. Enabling Technologies for 3-D Integration (edited by C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)

    Google Scholar 

  58. Nain, R., Chrzanowska-Jeske, M.: Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(9), 1667–1680 (2011)

    Google Scholar 

  59. Panda, P.R., Catthoor, F., Dutt, N.D., Danckaert, K., Brockmeyer, E., Kulkarni, C., Kjeldsberg, P.G.: Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems 6, 149–206 (2001)

    Article  Google Scholar 

  60. Po, L.M., Ma, W.C.: A novel four-step search algorithm for fast block motion estimation. IEEE Trans. on Circuits and Systems for Video Technology 6, 313–317 (1996)

    Article  Google Scholar 

  61. Pozder, S., Chatterjee, R., Jain, A., Huang, Z., Jones, R., Acosta, E.: Progress of 3D Integration Technologies and 3D Interconnects. In: Proc. of IEEE International Interconnect Technology Conference, pp. 213–215 (2007)

    Google Scholar 

  62. Pozder, S., Jones, R., Adams, V., Li, H.F., Canonico, M., Zollner, S., Lee, S., Gutmann, R., Lu, J.Q.: Exploration of the scaling limits of 3d integration. Enabling Technologies for 3-D Integration (edited by C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)

    Google Scholar 

  63. Rickert, P., Krenik, W.: Cell phone integration: SiP, SoC, and PoP. IEEE Design & Test of Computers 23, 188–195 (2006)

    Article  Google Scholar 

  64. Ryu, S.K., Lu, K.H., Zhang, X., Im, J.H., Ho, P., Huang, R.: Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects. IEEE Transactions on Device and Materials Reliability 11(1), 35–43 (2011)

    Article  Google Scholar 

  65. Saen, M., Osada, K., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., Kuroda, T.: 3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE Journal of Solid-State Circuits 45(4), 856–862 (2010)

    Article  Google Scholar 

  66. Sapatnekar, S.: Addressing thermal and power delivery bottlenecks in 3D circuits. In: Proc. of Asia and South Pacific Design Automation Conference, pp. 423–428 (2009)

    Google Scholar 

  67. Seiculescu, C., Murali, S., Benini, L., De Micheli, G.: SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(12), 1987–2000 (2010)

    Article  Google Scholar 

  68. SEMATECH Consortium. http://www.sematech.org

  69. Strauss, W.: The real DSP chip market. IEEE Signal Processing Magazine 20, 83 (2003)

    Article  Google Scholar 

  70. Tham, J.Y., Ranganath, S., Ranganath, M., Kassim, A.A.: A novel unrestricted center-biased diamond search algorithms for block motion estimation. IEEE Trans. on Circuits and Systems for Video Technology 8, 369–377 (1998)

    Article  Google Scholar 

  71. Tham, J.Y., Ranganath, S., Ranganath, M., Kassim, A.A.: A new diamond search algorithm for fast block-matching motion estimation. IEEE Trans. on Image processing 9, 287–290 (2000)

    Article  Google Scholar 

  72. Sveriges Television (SVT). http://www.svt.se

  73. Wang, K.T., Chen, O.C.: Motion estimation using an efficient four-step search method. In: Proc. of IEEE International Symposium on Circuits and Systems, pp. 217–220 (1998)

    Google Scholar 

  74. Wang, R., Li, J., Huang, C.: Motion compensation memory access optimization strategies for H.264/AVC decoder. In: Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 97–100 (2005)

    Google Scholar 

  75. Wiegand, T., Sullivan, G.J., Bjontegaard, G., Luthra, A.: Overview of the H.264/AVC video coding standard. IEEE Trans. on Circuits and Systems on Video Technology 13(7), 560–576 (2003)

    Google Scholar 

  76. Wu, Q., Zhang, T.: Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(9), 1655–1666 (2011)

    Google Scholar 

  77. Wu, Z., Wolf, W.: Design study of shared memory in vliw video signal processors. In: Proceedings of the 1998 International Conference onParallel Architectures and Compilation Techniques, pp. 52–59 (1998)

    Google Scholar 

  78. Wulf, W.A., McKee, S.A.: Hitting the MemoryWall: Implications of the Obvious. Computer Architecture News 23, 20–24 (1995)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Tong Zhang .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Zhang, T., Pan, Y., Li, Y. (2013). DSP Systems Using Three-Dimensional Integration Technology. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_26

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-6859-2_26

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-6858-5

  • Online ISBN: 978-1-4614-6859-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics