Abstract
Netlists describe circuits in a textual list format. They are normally of structural type and have two main targets:
-
Enumeration of all devices (or parts) including the input and output pins;
-
Enumeration of all connections between the device pins.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Tuinenga, P. W.: ‘SPICE, A Guide to Circuit Simulation & Analysis Using PSPICE’.–Englewood Cliffs, NJ: Prentice Hall, 1992
EDIF, Electronic Design Interchange Format, Version 2 0 0’. EIA EDIF Steering Committee, 1989
EDIF Technical Centre: http://www.edif.org
Accellera Interest Group: http://www.ovi.org
Standard Delay Format Specification, Version 2.1. Open Verilog International: http://www.eda.org
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media New York
About this chapter
Cite this chapter
Voland, G. (2003). Tabular Design Formats. In: Jansen, D. (eds) The Electronic Design Automation Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73543-6_8
Download citation
DOI: https://doi.org/10.1007/978-0-387-73543-6_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5369-8
Online ISBN: 978-0-387-73543-6
eBook Packages: Springer Book Archive