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Design for Testability

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The Electronic Design Automation Handbook

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Abstract

This section gives an overview of various aspects of testing chips. It considers the modeling of errors, automatic test pattern generation, and how to design circuits that can easily been tested. Usually in ASIC design systems there are special tools for supporting the testing of chips. Examples are the programs Quick-Fault and Fast-Scan from Mentor Graphics, Verifault from Cadence and TestCompiler from Synopsys. Additionally, synthesis tools typically support Scan Path and Boundary Scan techniques (sections 15.5 and 15.7). Section 15.6 gives some more specialized test structures which may be implemented by the chip designer, or are already part of parameterized cell generators.

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Authors
  1. Wolfgang Rülling
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Editors and Affiliations

  1. University of Applied Sciences, Offenburg, Germany

    Dirk Jansen (Director of ASIC Design Center) (Director of ASIC Design Center)

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© 2003 Springer Science+Business Media New York

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Rülling, W. (2003). Design for Testability. In: Jansen, D. (eds) The Electronic Design Automation Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73543-6_15

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  • DOI: https://doi.org/10.1007/978-0-387-73543-6_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5369-8

  • Online ISBN: 978-0-387-73543-6

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