Abstract
In this paper, we address the architectural synthesis for dynamically reconfigurable logic (DRL). We focus on a scheduling problem, which has a mandatory impact on quality of the final design. An efficient heuristic algorithm is presented, which searches for an optimal solution for DRL scheduling. The results from our experiments are demonstrated on an elliptic wave filter high-level synthesis benchmark. We also discuss register allocation and resource sharing problems for DRL architectural synthesis.
Keywords
- List Schedule
- Register Allocation
- Reconfigurable Hardware
- Reconfigurable Architecture
- Partial Reconfiguration
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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© 1996 Springer-Verlag Berlin Heidelberg
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Vasilko, M., Ait-Boudaoud, D. (1996). Architectural synthesis techniques for dynamically reconfigurable logic. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_31
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DOI: https://doi.org/10.1007/3-540-61730-2_31
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Online ISBN: 978-3-540-70670-0
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