Abstract
We discuss the design of a high performance constant coefficient multiplier on the Xilinx XC6200 FPGA. The dynamic reconfiguration capabilities of the device are used to allow the constant coefficient to be rapidly changed. The design also provides better performance and density than similar multipliers on state of the art conventional FPGA's which require complete reconfiguration to change the coefficient.
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References
Xilinx Inc, “XC6200 FPGA Family Advanced Product Description”, Available from Xilinx Inc. 2100 Logic Drive San Jose CA.
Wayne Luk and Nabeel Shirazi, “Modelling and Optimising Run Time Reconfigurable Systems”, Proc. IEEE Symposium on FPGA's for Custom Computing Machines, Napa CA 1996.
Tom Kean, “Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation” Phd Thesis CST-62-89, University of Edinburgh, Dept. Computer Science.
Tom Kean and John Gray, “Configurable Hardware: A New Paradigm for Computation”, Advanced Research in VLSI, Proc. Decennial Caltech Conference, MIT Press 1989.
Ken Chapman, “Fast Integer Multipiers fit in FPGA's”, EDN 1993 Design Idea Winner, EDN May 12th 1994.
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© 1996 Springer-Verlag Berlin Heidelberg
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Kean, T., New, B., Slous, B. (1996). A fast constant coefficient multiplier for the XC6200. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_24
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DOI: https://doi.org/10.1007/3-540-61730-2_24
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