Abstract
Logic emulation based on FPGAs became one of the major techniques of rapid prototyping. Such emulators allow a precise representation of the system's behaviour but unfortunately the timing can not be mapped precisely. This paper presents an approach to include a slow motion functionality into a FPGA-based emulation, that allows the emulator to reflect precisely the timing of the final system.
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© 1996 Springer-Verlag Berlin Heidelberg
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Janzen, N., Rammig, F.J. (1996). A slow motion engine for the analysis of FPGA-based prototypes. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_22
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DOI: https://doi.org/10.1007/3-540-61730-2_22
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Online ISBN: 978-3-540-70670-0
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