Computing 2-D DFTs using FPGAs

Abstract

Considerable success has been achieved in developing signal processing algorithms that are efficient from the standpoint of number of operations. However, what is needed now is to develop new algorithms which are better adapted to existing hardware, or to devise new architectures that more efficiently exploit existing signal processing algorithms. This latter approach forms the basis of this paper. An FPGA architecture is described that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. The performance of the architecture is presented and is shown to use 31% less FPGA resources than a row-column DFT processor. A multi-FPGA architecture is described that is capable of processing 24 512 × 512-pixel images per second. The multi-FPGA processor is 38% more area efficient than a row-column DFT implementation.