Abstract
This paper describes the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH®) family of PLDs. With an advanced 0.65um technology and an innovative architecture, the next generation MACH family offers gale density up to 10,000+ gates with 100% routability, flexibility, and predictable worst-case pin-to-pin delays of 15ns.
This is a preview of subscription content, log in via an institution.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1994 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Agrawal, O.P. (1994). A high density complex PLD family optimized for flexibility, predictability and 100% routability. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_105
Download citation
DOI: https://doi.org/10.1007/3-540-58419-6_105
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-58419-3
Online ISBN: 978-3-540-48783-8
eBook Packages: Springer Book Archive