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International Conference on Parallel Architectures and Languages Europe

PARLE 1994: PARLE'94 Parallel Architectures and Languages Europe pp 336–350Cite as

Analytic model of a Cache Only Memory Architecture

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 817))

Abstract

An approximate analytic model of a shared memory multiprocessor with a Cache Only Memory Architecture (COMA), the bus-based Data Difussion Machine (DDM), is presented and validated. It describes the timing and interference in the system as a function of the hardware, the protocols, the topology and the workload. Model results have been compared to results from an independent simulator. The comparison shows good model accuracy specially for non-saturated systems, where the errors in response times and device utilizations are independent of the number of processors and remain below 10% in 90% of the simulations. Therefore, the model can be used as an average performance prediction tool that avoids expensive simulations in the design of systems with many processors.

This work was funded in part by ESPRIT project 2471 and by CAM project 066/92

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References

  1. H. Burkhardt, S. Frank, B. Knobe, and J. Rothnie. Overview of the KSR1 Computer System. Technical Report KSR-TR-9202001, Kendall Square Research, 1992.

    Google Scholar 

  2. C. Carreras. Modelo Analítico de la Máquina de Difusión de Datos y Efecto de la Inclusión de Procesadores Multicontexto. PhD thesis, E.T.S.I.Telecomunicación, Universidad Politécnica de Madrid, Sep 1993.

    Google Scholar 

  3. E. Hagersten, P. Anderson, A. Landin, and S. Haridi. A Performance Study of the DDM — A Cache Only Memory Architecture. Technical Report R91:17, Swedish Institute of Computer Science, Nov 1991.

    Google Scholar 

  4. E. Hagersten, S. Haridi, and D. H. D. Warren. The Cache-Coherence Protocol of the Data Diffusion Machine. In M. Dubois and S. S. Thakkar, editors, Cache and Interconnect Architectures in Multiprocessors. Kluwer Academic Publisher, 1990.

    Google Scholar 

  5. E. Hagersten, A. Landin, and S. Haridi. DDM — A Cache-Only Memory Architecture. IEEE Computer, 25(9):44–54, 1991.

    Google Scholar 

  6. L. Kleinrock. Queueing Systems (Volumes 1 and 2). John Wiley and Sons, 1975.

    Google Scholar 

  7. E. D. Lazowska, J. Zahorjan, G. S. Graham, and K. C. Sevcik. Quantitative System Performance — Computer System Analysis Using Queueing Network Models. Prentice-Hall, 1984.

    Google Scholar 

  8. M. Lofgren. A Simulator in C++ for a Parallel Architecture. PhD thesis, Swedish Institute of Computer Science, Nov 1990.

    Google Scholar 

  9. A. Norton and G. F. Pfister. A Methodology for Predicting Multiprocessor Performance. In Proceedings 15th Annual International Symposium on Parallel Processing, pages 772–781, 1985.

    Google Scholar 

  10. S. Raina and D. H. D. Warren. Traffic Patterns in a Scalable Multiprocessor through Transputer Emulation. In Proceedings International Hawaii Conference on System Science, 1991.

    Google Scholar 

  11. J. P. Singh, W.-D. Weber, and A. Gupta. SPLASH: Stanford Parallel Applications for Shared-Memory. Technical Report CSL-TR-92-526, Computer Systems Laboratory, Stanford University, Jun 1992.

    Google Scholar 

  12. M. K. Vernon, R. Jog, and G. S. Sohi. Performance Analysis of Hierarchical Cache-Consistent Multiprocesors. In Proceedings International Seminar on Performance of Distributed and Parallel Systems, pages 111–126. North-Holland, Dec 1988.

    Google Scholar 

  13. D. H. D. Warren and S. Haridi. Data Diffusion Machine — A Scalable Shared Virtual Memory Multiprocessor. In International Conference on Fifth Generation Computer Systems. ICOT, 1988.

    Google Scholar 

  14. A. W. Wilson. Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. In Proceedings 14th Annual Symposium on Computer Architecture, pages 244–252, 1987.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Departamento de Ingeniería Electrónica, Universidad Politécnica de Madrid, Ciudad Universitaria s/n, 28040, Madrid, Spain

    Carlos Carreras & Carlos A. López

  2. Departamento de Inteligencia Artificial, Universidad Politécnica de Madrid, Boadilla del Monte, 28660, Madrid, Spain

    Manuel Hermenegildo

Authors
  1. Carlos Carreras
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  2. Carlos A. López
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  3. Manuel Hermenegildo
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Editor information

Costas Halatsis Dimitrios Maritsas George Philokyprou Sergios Theodoridis

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© 1994 Springer-Verlag Berlin Heidelberg

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Carreras, C., López, C.A., Hermenegildo, M. (1994). Analytic model of a Cache Only Memory Architecture. In: Halatsis, C., Maritsas, D., Philokyprou, G., Theodoridis, S. (eds) PARLE'94 Parallel Architectures and Languages Europe. PARLE 1994. Lecture Notes in Computer Science, vol 817. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58184-7_113

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  • DOI: https://doi.org/10.1007/3-540-58184-7_113

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58184-0

  • Online ISBN: 978-3-540-48477-6

  • eBook Packages: Springer Book Archive

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