Abstract
A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. A layered PMC is a PMC in which all input nodes are in the external face, and the gates can be assigned to layers in such a way that every wire goes between gates in successive layers. Goldschlager, Cook & Dymond and others have developed NC 2 algorithms to evaluate a layered PMC when the output node is in the same face as the input nodes. These algorithms require a large number of processors (Ω(n 6), where n is the size of the input circuit). In this paper, we give an efficient parallel algorithm that evaluates a layered PMC of size n in O(log2 n) time using only a linear number of processors on an EREW PRAM. Our parallel algorithm is the best possible to within a polylog factor, and is a substantial improvement over the earlier algorithms for the problem.
This work was supported by Texas Advanced Research Program Grant 003658480 and NSF Grant CCR 90-23059.
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Ramachandran, V., Yang, H. (1993). An efficient parallel algorithm for the layered planar monotone circuit value problem. In: Lengauer, T. (eds) Algorithms—ESA '93. ESA 1993. Lecture Notes in Computer Science, vol 726. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57273-2_67
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DOI: https://doi.org/10.1007/3-540-57273-2_67
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