Abstract
In 1984 Kramer and van Leeuwen proved a fundamental complexity result of VLSI layout theory. They showed that the so-called General Layout Problem, i.e. the problem of embedding a graph into a grid of minimum area is NP-hard, even for connected (but not necessarily planar) graphs.
VLSI circuits (or large parts of them) are typically modelled by planar graphs, but Kramer and van Leeuwen used a family of non-planar graphs for their reduction and they posed the complexity of minimum area layouts of planar connected graphs as an open problem.
We
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close a gap in their proof,
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extend the NP-hardness result to the more realistic class of planar connected graphs and
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show this for three different embedding models, including the Manhattan and the knock-knee model.
Keywords
This work was partially supported by the ESPRIT II Basic Research Actions Program of the EC under contract no. 3075 (project ALCOM).
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References
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© 1991 Springer-Verlag Berlin Heidelberg
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Formann, M., Wagner, F. (1991). The VLSI layout problem in various embedding models. In: Möhring, R.H. (eds) Graph-Theoretic Concepts in Computer Science. WG 1990. Lecture Notes in Computer Science, vol 484. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53832-1_38
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DOI: https://doi.org/10.1007/3-540-53832-1_38
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