SOI-CMOS compatibility validation

4.6 Conclusions

We revealed in the introduction that the additive steps at the beginning of the standard CMOS SOI process (to provide the second layer of our membrane in LPCVD nitride) did not affect the performances of our transistors. This was expected since these steps were achieved far enough from the integrated circuits. With the transistors on membrane, we demonstrated that these processing steps can also be advantageously combined to the IC fabrication without altering the CMOS compatibility.

We demonstrated also the full compatibility of our post-processing not only in the case of gas flow sensors on membrane working close to the electronics but in the case of transistors suspended on membrane too. Nevertheless, we showed and discussed the limitations of the full compatibility when metallic layers need to be evaporated near to large electronics. Our measurements revealed also that TMAH introduces a slight leakage current increase which can be canceled by a dedicated annealing.

Therefore, the full SOI CMOS compatibility of our process was demonstrated. This confirms that our gas flow sensors are ready to be co-integrated in the same chip to feature smart microsystems. Furthermore, we introduced for the first time the ability to co-integrate high performance transistors on dielectric membrane, which can open the door to a large kind of sensors applications, such as pressure, gasFET or temperature sensors.