Network-on-Chip for Multi- and Many-Core Systems

Abstract

The advance of the semiconductor technology allows us to integrate a number of IP cores such as processors, caches, and I/O modules on a single chip. To connect these cores, Network-on-Chip (NoC) that introduces a packet switched network has been widely studied and used in various types of commercial chips that include cost-effective embedded devices. Such applications often demand very tight design constraints in terms of cost and performance; thus the silicon budget available for their on-chip network should be modest. In addition, power consumption is a crucial factor, since it affects their battery life or packaging costs for heat dissipation. In this chapter, we explain low-power and low-cost on-chip architectures in terms of router architecture, network topology, and routing for multi- and many-core systems.