Abstract
This paper addresses the problem of how to schedule periodic, real-time threads on a class of architectures referred, to as multilevel-context (MLC) architectures. Examples of such architectures are real-time operating systems with support for user- or kernel-level threads, and multithreaded microprocessors endowed with on-chip contexts. A common feature of these architectures is that they provide support for the administration of threads within contexts at different levels of abstraction. Therefore, the cost for switching between threads will depend on the affinity of their corresponding contexts. The main contributions of this paper are to demonstrate (i) how the scheduling performance for off-line scheduling on MLC architectures can benefit from an integrated heuristic that is cognizant of both the time-criticality of a thread and the current context affinity; and (ii) how the predicted performance for on-line scheduling on MLC architectures can benefit from an off-line schedulability test that accounts for variations in the context affinity.
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C. A. Healy, D. B. Whalley, and M. G. Harmon, “Integrating the Timing Analysis of Pipelining and Instruction Caching”, Proc. of the IEEE Real-Time Systems Symposium, Pisa, Italy, Dec. 5–7, 1995, pp. 288–297.
R. T. White, F. Mueller, C. A. Healy, D. B. Whalley, and M. G. Harmon, “Timing Analysis for Data Caches and Set-Associative Caches”, Proc. of the IEEE Real-Time Technology and Applications Symposium, Montreal, Canada, June 9–11, 1997, pp. 192–202.
C. L. Liu and J. W. Layland, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment”, Journal of the Association for Computing Machinery, vol. 20, no. 1, pp. 46–61, Jan. 1973.
D. I. Katcher, H. Arakawa, and J. K. Strosnider, “Engineering and Analysis of Fixed Priority Schedulers”, IEEE Trans. on Software Engineering, vol. 19, no. 9, pp. 920–934, Sept. 1993.
M. Humphrey, G. Wallace, and J. A. Stankovic, “Kernel-Level Threads for Dynamic, Hard Real-Time Environments”, Proc. of the IEEE Real-Time Systems Symposium, Pisa, Italy, Dec. 5–7, 1995, pp. 38–48.
S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen, “Simultaneous Multithreading: A Platform for Next-Generation Processors”, IEEE Micro, vol. 17, no. 5,. pp. 12–19, Sept./Oct. 1997.
K. Diefendorff and P. K. Dubey, “How Multimedia Workloads will Change Processor Design”, IEEE Computer, vol. 30, no. 9, pp. 43–45, Sept. 1997.
A. Agarwal, J. Kubiatowicz, D. Kranz, B.-H. Lim, D. Yeung, G. D’Souza, and M. Parkin, “Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors”, IEEE Micro, vol. 13, no. 3, pp. 48–61, June 1993.
S. Fiske and W. J. Dally, “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”, Proc. of the IEEE Symposium on High Performance Computer Architecture, Raleigh, North Carolina, Jan. 22–25, 1995, pp. 210–221.
C. A. Waldspurger and W. E. Weihl, “Register Relocation: Flexible Contexts for Multithreading”, Proc. of the ACM Int’l Symposium on Computer Architecture, San Diego, California, May 16–19, 1993, pp. 120–130.
J. Jonsson, “GAST: A Flexble and Extensible Tool for Evaluating, Multiprocessor Assignment and Scheduling Techniques”, Proc. of the Int’l Conf. on Parallel Processing, Minneapolis, Minnesota, Aug. 10–14, 1998, pp. 441–450.
C.-Y. Lee, J.-J. Hwang, Y.-C. Chow,and F. D. Anger, “Multiprocessor, Scheduling with Interprocessor Communication Delays”, Operations Research Letters, vol. 7, no. 3, pp. 141–147, June 1988.
B.-C. Cheng, A. D. Stoyenko, T. J. Marlowe, and S. Baruah, “A Scheduler Maximizing Maximum Tardiness for DSP Programs with Context Switch Overheads Considered”, Proc. of the Int’l Conf. on Signal Processing, Applications & Technology, Boston, Massachusetts, Oct. 7–10, 1996, pp. 771–775.
Q. Zheng and K. G. Shin, “On the Ability of Establishing Real-Time Channels in Point-to-Point Packet-Switched Networks”, IEEE Trans. on Communications, vol. 42, no. 2/3/4, pp. 1096–1105, Feb./Mar./Apr. 1994.
J. Jonsson, H. Lönn, and K. G. Shin, “Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures” Technical Report No. 98-6, Dept. of Computer Engineering, Chalmers University of Technology, S-412 96 Göteborg, Sweden, May 1998.
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© 1999 Springer-Verlag
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Jonsson, J., Lönn, H., Shin, K.G. (1999). Non-preemptive scheduling of real-time threads on multi-level-context architectures. In: Rolim, J., et al. Parallel and Distributed Processing. IPPS 1999. Lecture Notes in Computer Science, vol 1586. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0097918
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DOI: https://doi.org/10.1007/BFb0097918
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