Skip to main content

Non-preemptive scheduling of real-time threads on multi-level-context architectures

  • Conference paper
  • First Online:
Parallel and Distributed Processing (IPPS 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1586))

Included in the following conference series:

Abstract

This paper addresses the problem of how to schedule periodic, real-time threads on a class of architectures referred, to as multilevel-context (MLC) architectures. Examples of such architectures are real-time operating systems with support for user- or kernel-level threads, and multithreaded microprocessors endowed with on-chip contexts. A common feature of these architectures is that they provide support for the administration of threads within contexts at different levels of abstraction. Therefore, the cost for switching between threads will depend on the affinity of their corresponding contexts. The main contributions of this paper are to demonstrate (i) how the scheduling performance for off-line scheduling on MLC architectures can benefit from an integrated heuristic that is cognizant of both the time-criticality of a thread and the current context affinity; and (ii) how the predicted performance for on-line scheduling on MLC architectures can benefit from an off-line schedulability test that accounts for variations in the context affinity.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. C. A. Healy, D. B. Whalley, and M. G. Harmon, “Integrating the Timing Analysis of Pipelining and Instruction Caching”, Proc. of the IEEE Real-Time Systems Symposium, Pisa, Italy, Dec. 5–7, 1995, pp. 288–297.

    Google Scholar 

  2. R. T. White, F. Mueller, C. A. Healy, D. B. Whalley, and M. G. Harmon, “Timing Analysis for Data Caches and Set-Associative Caches”, Proc. of the IEEE Real-Time Technology and Applications Symposium, Montreal, Canada, June 9–11, 1997, pp. 192–202.

    Google Scholar 

  3. C. L. Liu and J. W. Layland, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment”, Journal of the Association for Computing Machinery, vol. 20, no. 1, pp. 46–61, Jan. 1973.

    MATH  MathSciNet  Google Scholar 

  4. D. I. Katcher, H. Arakawa, and J. K. Strosnider, “Engineering and Analysis of Fixed Priority Schedulers”, IEEE Trans. on Software Engineering, vol. 19, no. 9, pp. 920–934, Sept. 1993.

    Article  Google Scholar 

  5. M. Humphrey, G. Wallace, and J. A. Stankovic, “Kernel-Level Threads for Dynamic, Hard Real-Time Environments”, Proc. of the IEEE Real-Time Systems Symposium, Pisa, Italy, Dec. 5–7, 1995, pp. 38–48.

    Google Scholar 

  6. S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen, “Simultaneous Multithreading: A Platform for Next-Generation Processors”, IEEE Micro, vol. 17, no. 5,. pp. 12–19, Sept./Oct. 1997.

    Article  Google Scholar 

  7. K. Diefendorff and P. K. Dubey, “How Multimedia Workloads will Change Processor Design”, IEEE Computer, vol. 30, no. 9, pp. 43–45, Sept. 1997.

    Google Scholar 

  8. A. Agarwal, J. Kubiatowicz, D. Kranz, B.-H. Lim, D. Yeung, G. D’Souza, and M. Parkin, “Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors”, IEEE Micro, vol. 13, no. 3, pp. 48–61, June 1993.

    Article  Google Scholar 

  9. S. Fiske and W. J. Dally, “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”, Proc. of the IEEE Symposium on High Performance Computer Architecture, Raleigh, North Carolina, Jan. 22–25, 1995, pp. 210–221.

    Google Scholar 

  10. C. A. Waldspurger and W. E. Weihl, “Register Relocation: Flexible Contexts for Multithreading”, Proc. of the ACM Int’l Symposium on Computer Architecture, San Diego, California, May 16–19, 1993, pp. 120–130.

    Google Scholar 

  11. J. Jonsson, “GAST: A Flexble and Extensible Tool for Evaluating, Multiprocessor Assignment and Scheduling Techniques”, Proc. of the Int’l Conf. on Parallel Processing, Minneapolis, Minnesota, Aug. 10–14, 1998, pp. 441–450.

    Google Scholar 

  12. C.-Y. Lee, J.-J. Hwang, Y.-C. Chow,and F. D. Anger, “Multiprocessor, Scheduling with Interprocessor Communication Delays”, Operations Research Letters, vol. 7, no. 3, pp. 141–147, June 1988.

    Article  MATH  MathSciNet  Google Scholar 

  13. B.-C. Cheng, A. D. Stoyenko, T. J. Marlowe, and S. Baruah, “A Scheduler Maximizing Maximum Tardiness for DSP Programs with Context Switch Overheads Considered”, Proc. of the Int’l Conf. on Signal Processing, Applications & Technology, Boston, Massachusetts, Oct. 7–10, 1996, pp. 771–775.

    Google Scholar 

  14. Q. Zheng and K. G. Shin, “On the Ability of Establishing Real-Time Channels in Point-to-Point Packet-Switched Networks”, IEEE Trans. on Communications, vol. 42, no. 2/3/4, pp. 1096–1105, Feb./Mar./Apr. 1994.

    Article  Google Scholar 

  15. J. Jonsson, H. Lönn, and K. G. Shin, “Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures” Technical Report No. 98-6, Dept. of Computer Engineering, Chalmers University of Technology, S-412 96 Göteborg, Sweden, May 1998.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

José Rolim Frank Mueller Albert Y. Zomaya Fikret Ercal Stephan Olariu Binoy Ravindran Jan Gustafsson Hiroaki Takada Ron Olsson Laxmikant V. Kale Pete Beckman Matthew Haines Hossam ElGindy Denis Caromel Serge Chaumette Geoffrey Fox Yi Pan Keqin Li Tao Yang G. Chiola G. Conte L. V. Mancini Domenique Méry Beverly Sanders Devesh Bhatt Viktor Prasanna

Rights and permissions

Reprints and permissions

Copyright information

© 1999 Springer-Verlag

About this paper

Cite this paper

Jonsson, J., Lönn, H., Shin, K.G. (1999). Non-preemptive scheduling of real-time threads on multi-level-context architectures. In: Rolim, J., et al. Parallel and Distributed Processing. IPPS 1999. Lecture Notes in Computer Science, vol 1586. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0097918

Download citation

  • DOI: https://doi.org/10.1007/BFb0097918

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65831-3

  • Online ISBN: 978-3-540-48932-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics