Abstract
This work takes a different approach to synthesize a synchronous sequential logic circuit. The input of the synthesizer is a partial input/output sequence. This type of specification is not suitable for conventional synthesis methods. Genetic Algorithm (GA) was applied to synthesize the desired circuit that performs according to the input/output sequences. GA searches for circuits that represent the desired state transition function. Additional combination circuits that map states to the corresponding outputs are synthesized by conventional methods. The target of our synthesis is a type of registered Programmable Array Logic which is commercially available as GAL. We are able to synthesize various types of synchronous sequential logic circuit such as counter, serial adder, frequency divider, modulo-5 detector and parity checker.
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Manovit, C., Aporntewan, C., Chongstitvatana, P. (1998). Synthesis of synchronous sequential logic circuits from partial input/output sequences. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds) Evolvable Systems: From Biology to Hardware. ICES 1998. Lecture Notes in Computer Science, vol 1478. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0057611
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DOI: https://doi.org/10.1007/BFb0057611
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