Abstract
Field programmable gate array based computing machines have successfully demonstrated the performance advantages for a large class of compute intense problems. However, in most of the applications executing on FPGA based reconfigurable hardwares, the burden of careful design and mapping rests on the end user. Motivated with the task of making reconfigurable and adaptive computing more comprehensible to a software programmer, we have defined the REACT architecture. REACT consists of a dynamically and partially reconfigurable hardware platform supported by a collection of advanced analysis, compilation, and scheduling tools to allow maximum reconfigurability exploitation. The tools supporting REACT computing environment are portable to support other forms of reconfigurable processing hardware units. In other words, the tools completely hide the implementation details of a particular function in the hardware.
This research is partially supported by contract number DABT63-97-C-0029 from Defense Advanced Research Projects Agency (DARPA) and contract number F33615-96-C1912 from Wright Laboratory of the United States Air Force.
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Bhatia, D., Kannan, P., Simha, K.S., Gajjala Purna, K.M. (1998). REACT: Reactive environment for runtime reconfiguration. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055248
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DOI: https://doi.org/10.1007/BFb0055248
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