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Putting inner loops automatically in silicon

  • Chapter 3 VLSI Algorithms
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VLSI Engineering

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 163))

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Abstract

Many of the time consuming inner loops are inherently regular and parallel. These are exactly the structures that are well suited for VLSI implementation. As a result, it will become increasingly common to have subroutines that are directly executeable in silicon. Does it imply that in the near future many large computations can be effectively carried out by small computers equipped with silicon subroutines? This talk will present a simplied characterization of the silicon subroutine approach, and discuss systolic architectures—a powerful method for implementing cost-effective silicon subroutines for computations such as pattern matching and error-correcting. CAD systems at CMU that have made it possible for us to design some rather complex chips, such as a programmable systolic chip, will also be briefly described.

The research was supported in part by the Office of Naval Research under Contracts N00014-76-C-0370, NR 044-422 and N00014-80-C-0236, NR 048-659, and in part by the Defense Advanced Research Projects Agency (DOD), ARPA Order No. 3597, monitored by the Air Force Avionics Laboratory under Contract F33615-81-K-1539.

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  1. Department of Computer, Carnegie-Mellon University, 15213, Pittsburgh, Pennsylvania, USA

    H. T. Kung

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  1. H. T. Kung
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Tosiyasu L. Kunii

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© 1984 Springer-Verlag Berlin Heidelberg

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Kung, H.T. (1984). Putting inner loops automatically in silicon. In: Kunii, T.L. (eds) VLSI Engineering. Lecture Notes in Computer Science, vol 163. Springer, Tokyo. https://doi.org/10.1007/BFb0043449

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  • DOI: https://doi.org/10.1007/BFb0043449

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  • Print ISBN: 978-4-431-70002-9

  • Online ISBN: 978-4-431-36817-5

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