Data flow programming for parallel implementation of digital signal processing systems

Abstract

Digital signal processing systems constitute a special class of discrete event systems where events correspond to samples of signals. A data flow description of such systems can capture much of the information required for high performance, cost-effective, parallel implementation. A formal model called synchronous data flow (SDF) is a useful special case of data flow and subclass of discrete event systems where the events are deterministic and periodic. An SDF description of an algorithm can be first analyzed for implementability, then an implementation can be synthesized. In the analysis phase we can check for (1) stability of the buffers, (2) freedom from deadlocks, and (3) adequate concurrency to meet a given performance specification. The synthesis phase consists primarily of constructing a periodic schedule and mapping the algorithm onto parallel processors. The resulting schedule is said to be static and is far less costly to implement than dynamic, or run-time scheduling.

Although many digital signal processing systems can be accurately described within the SDF model, the model needs to be generalized to be broadly applicable. In particular, the expanded model should accommodate asynchronous systems and systems with data dependent computations. To some degree, dynamic scheduling becomes essential. However, in order to achieve high performance and low cost, fully dynamic scheduling should be avoided. Limited extensions to the SDF model are described which are inexpensive to implement and can be used to describe a variety of systems with asynchronous events.

This research was sponsored by an IBM faculty development grant and National Science Foundation Presidential Young Investigator award.