Abstract
In this paper we introduce a general framework for compaction on a torus. This problem comes up whenever an array or row of identical cells has to be compacted. We instantiate our framework with several specific compaction algorithms: one-dimensional compaction without and with automatic jog insertion and two-dimensional compaction.
This research was supported by the DFG, grant SFB 124, TP B2
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V. References
Cole, R., and Siegel, A., “River routing every which way, but loose”, Proceedings of the 25th Annual Symposium on Foundations of Computer Science, October 1984, pp. 65–73
Dunlop, A.E., “SLIP: symbolic layout of integrated circuits with compaction”, Computer Aided Design, Vol. 10, No. 6, 1978, pp. 387–391
Eichenberger, P., and Horowitz, M., “Toroidal Compaction of Symbolic Layouts for Regular Structures”, 1987 IEEE, ICCAD, pp. 142–145
Hsueh, M.Y., “Symbolic Layout and Compaction of Integrated Circuits”, Ph.D. theis, EECS Divisio, University of California, Berkeley, 1979
Gao, S., Jerrum, M., Kaufmann, M., Mehlhorn, K., Rülling, W., Storb, C., “On homotopic river routing”, BFC 87, Bonn, 1987
Kaufmann, M., and Mehlhorn, K., “Local Routing of Two-Terminal Nets”, 4th STACS 87, LNCS 247, pp. 40–52
Kedem, G., and Watanabe, H., “Optimization techniques for IC layout and compaction”, Technical Report 117, Computer Science Department, University of Rochester, 1982
Leiserson, C.E., and Maley, F.M., “Algorithms for routing and testing routability of planar VLSI layouts”, Proceedings of the 17th Annual ACM Symposium on Theory of Computing, 1985, pp. 69–78
Leiserson, C.E., and Pinter, R.Y., “Optimal placement for river routing”, SIAM Journal on Computing, Vol. 12, No. 3, 1983, pp. 447–462
Lengauer, T., “Efficient algorithms for the constraint generation for integrated circuit layout compaction”, Proceedings of the 9th Workshop on Graphtheoretic Concepts in Computer Science, 1983
Lengauer, T., and Mehlhorn, K., “The HILL system: a design environment for the hierarchical specification, compaction, and simulation for integrated circuit layouts”, Proceedings, Conference on Advanced Research in VLSI, 1984
Lengauer, T., “On the solution of inequality systems relevant to IC layout”, Journal of Algorithms, Vol. 5, No. 3, 1984, pp. 408–421
Lengauer, T., “The Complexity of Compacting Hierarchically Specified Layouts of Integrated Circuits”, 1982 FOCS, pp. 358–368
Lichter, P., “Ein Schaltkreis für die Kulischarithmetik”, Diplomarbeit, Universität des Saarlandes, 1988, in preparation
Maley, F.M., “Compaction with Automatic Jog Insertion”, 1985 Chapel Hill Conference on VLSI
Maley, F.M., “Single-Layer Wire Routing”, Ph.D. thesis, MIT, 1987
Mehlhorn, K., and Näher, St., “A Faster Compaction Algorithm with Automatic Jog Insertion”, Proceedings of the 1988 MIT VLSI Conference
Pinter, R.Y., “The Impact of Layer Assignment Methods on Layout Algorithms for Integrated Circuits”, Ph.D. thesis, MIT Department of Electrical Engineering and Computer Science, 1982
Rülling, W., “Einführung in die Chip-Entwurfssprache HILL”, Techn. Bericht 04/1987, SFB124, Univ. des Saarlandes, 1987
Williams, J.D., “STICKS — a graphical compiler for high level LSI design”, National Computer Conference, 1978, pp. 289–295
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© 1988 Springer-Verlag Berlin Heidelberg
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Mehlhorn, K., Rülling, W. (1988). Compaction on the torus. In: Reif, J.H. (eds) VLSI Algorithms and Architectures. AWOC 1988. Lecture Notes in Computer Science, vol 319. Springer, New York, NY. https://doi.org/10.1007/BFb0040389
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DOI: https://doi.org/10.1007/BFb0040389
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