Design of a viterbi decoder with microprocessor-based serial implementation
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The purpose of this paper is to present the design of a Viterbi decoder, for moderate data transmission rates (hundreds of bits/sec), using a serial implementation based on a 16/32-bit microprocessor.
This design is only one experimental phase of a final version which will be constructed to operate at a data transmission rate of 32 Kbits/sec, utilizing principally MECL and TTL integrated circuits.
KeywordsConvolutional Code Survivor Path Data Transmission Rate Viterbi Decoder Binary Symmetric Channel
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