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Design of a viterbi decoder with microprocessor-based serial implementation

  • F. J. García-Ugalde
  • R. H. Morelos-Zaragoza A
Conference paper
  • 136 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 307)

Abstract

The purpose of this paper is to present the design of a Viterbi decoder, for moderate data transmission rates (hundreds of bits/sec), using a serial implementation based on a 16/32-bit microprocessor.

This design is only one experimental phase of a final version which will be constructed to operate at a data transmission rate of 32 Kbits/sec, utilizing principally MECL and TTL integrated circuits.

Keywords

Convolutional Code Survivor Path Data Transmission Rate Viterbi Decoder Binary Symmetric Channel 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • F. J. García-Ugalde
    • 1
  • R. H. Morelos-Zaragoza A
    • 1
  1. 1.División de Estudios de Posgrado Facultad de Ingeniería, UNAMCd. UniversitariaMEXICO, DF

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