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International Conference on Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes

AAECC 1986: Applicable Algebra, Error-Correcting Codes, Combinatorics and Computer Algebra pp 58–67Cite as

Design of a viterbi decoder with microprocessor-based serial implementation

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 307))

Abstract

The purpose of this paper is to present the design of a Viterbi decoder, for moderate data transmission rates (hundreds of bits/sec), using a serial implementation based on a 16/32-bit microprocessor.

This design is only one experimental phase of a final version which will be constructed to operate at a data transmission rate of 32 Kbits/sec, utilizing principally MECL and TTL integrated circuits.

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References

  1. J.A. Heller and I.M. Jacobs, "Viterbi Decoding for Satellite and Space Communications", IEEE Trans. on Commun. Technol., Vol. COM-19, No. 5, Oct. 1971, pp. 835–848.

    Google Scholar 

  2. A.J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm", IEEE Trans. Inf. Theory, Vol. IT-13, Apr. 1967, pp. 260–269.

    Google Scholar 

  3. A.J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems", IEEE Trans. on Commun. Technol., Vol. COM-19, No. 5, Oct. 1971, pp. 751–772.

    Google Scholar 

  4. J.P. Odenwalder, "Optimal Decoding of Convolutional Codes", Ph.D. thesis, University of California, Los Angeles, 1970.

    Google Scholar 

  5. J.B. Cain, G.C. Clark Jr., and J.M. Geist, "Punctured Convolutional Codes of rate (n-1)/n and Simplified Maximum Likelihood Decoding", IEEE Trans. Inf. Theory, Vol. IT-25, No. 1, Jan. 1979, pp. 97–100.

    Google Scholar 

  6. C.M. Rader, "Memory Management in Viterbi Decoder", IEEE Trans. on Commun., Vol. COM-29, No. 9, Sep. 1981. pp. 1399–1401.

    Google Scholar 

  7. G.D. Forney, "The Viterbi Algorithm", Proc. IEEE, Vol. 61, Mar. 1973, pp. 268–277.

    Google Scholar 

  8. H.H. Ma, "The Multiple Stack Algorithm Implemented on a Zilog Z-80 Microcomputer", IEEE Trans. on Commun., Vol. COM-28, No. 11, Nov. 1980, pp. 1876–1882.

    Google Scholar 

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Author information

Authors and Affiliations

  1. División de Estudios de Posgrado Facultad de Ingeniería, UNAM, Cd. Universitaria, A.P. 70-256, 04510, MEXICO, DF

    F. J. García-Ugalde & R. H. Morelos-Zaragoza A

Authors
  1. F. J. García-Ugalde
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  2. R. H. Morelos-Zaragoza A
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Thomas Beth Michael Clausen

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© 1988 Springer-Verlag Berlin Heidelberg

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García-Ugalde, F.J., Morelos-Zaragoza A, R.H. (1988). Design of a viterbi decoder with microprocessor-based serial implementation. In: Beth, T., Clausen, M. (eds) Applicable Algebra, Error-Correcting Codes, Combinatorics and Computer Algebra. AAECC 1986. Lecture Notes in Computer Science, vol 307. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0039179

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  • DOI: https://doi.org/10.1007/BFb0039179

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-19200-8

  • Online ISBN: 978-3-540-39133-3

  • eBook Packages: Springer Book Archive

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