Design of a viterbi decoder with microprocessor-based serial implementation

  • F. J. García-Ugalde
  • R. H. Morelos-Zaragoza A
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 307)


The purpose of this paper is to present the design of a Viterbi decoder, for moderate data transmission rates (hundreds of bits/sec), using a serial implementation based on a 16/32-bit microprocessor.

This design is only one experimental phase of a final version which will be constructed to operate at a data transmission rate of 32 Kbits/sec, utilizing principally MECL and TTL integrated circuits.


Convolutional Code Survivor Path Data Transmission Rate Viterbi Decoder Binary Symmetric Channel 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    J.A. Heller and I.M. Jacobs, "Viterbi Decoding for Satellite and Space Communications", IEEE Trans. on Commun. Technol., Vol. COM-19, No. 5, Oct. 1971, pp. 835–848.Google Scholar
  2. [2]
    A.J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm", IEEE Trans. Inf. Theory, Vol. IT-13, Apr. 1967, pp. 260–269.Google Scholar
  3. [3]
    A.J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems", IEEE Trans. on Commun. Technol., Vol. COM-19, No. 5, Oct. 1971, pp. 751–772.Google Scholar
  4. [4]
    J.P. Odenwalder, "Optimal Decoding of Convolutional Codes", Ph.D. thesis, University of California, Los Angeles, 1970.Google Scholar
  5. [5]
    J.B. Cain, G.C. Clark Jr., and J.M. Geist, "Punctured Convolutional Codes of rate (n-1)/n and Simplified Maximum Likelihood Decoding", IEEE Trans. Inf. Theory, Vol. IT-25, No. 1, Jan. 1979, pp. 97–100.Google Scholar
  6. [6]
    C.M. Rader, "Memory Management in Viterbi Decoder", IEEE Trans. on Commun., Vol. COM-29, No. 9, Sep. 1981. pp. 1399–1401.Google Scholar
  7. [7]
    G.D. Forney, "The Viterbi Algorithm", Proc. IEEE, Vol. 61, Mar. 1973, pp. 268–277.Google Scholar
  8. [8]
    H.H. Ma, "The Multiple Stack Algorithm Implemented on a Zilog Z-80 Microcomputer", IEEE Trans. on Commun., Vol. COM-28, No. 11, Nov. 1980, pp. 1876–1882.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • F. J. García-Ugalde
    • 1
  • R. H. Morelos-Zaragoza A
    • 1
  1. 1.División de Estudios de Posgrado Facultad de Ingeniería, UNAMCd. UniversitariaMEXICO, DF

Personalised recommendations