A stochastic algorithm for circuit bi-partitioning
Circuit bi-partitioning is an important step in placement algorithms based on the min-cut paradigm. In this paper, we present a stochastic algorithm for circuit bi-partitioning (BIPART) which minimizes the number of nets cut while maintaining a tight control on the sizes of the two parts. BIPART performs better than simulated annealing and the Fiduccia-Matheyses algorithm, and runs in linear time per iteration.
KeywordsSimulated Annealing Design Automation Selection Step Stochastic Algorithm Placement Algorithm
Unable to display preview. Download preview PDF.
- M. Breuer, "Min-Cut Placement," J. Design Automation and Fault-Tolerant Computing, vol. 1, no. 4, pp. 343–362, Oct. 1977.Google Scholar
- Earl E. Barnes, "An Algorithm for Partitioning the Nodes of a Graph," IBM Technical Report RC8690, 1981.Google Scholar
- C. M. Fiduccia and R. M. Mattheyses, "A Linear-Time Heuristics for Improving Network Partitions," Proceedings of the 19th Design Automation Conference, pp. 175–181, January 1982.Google Scholar
- D. Schweikert and B. Kernighan, "A Proper Model for the Partitioning of Electrical Circuits," Proceedings of the 9th Design Automation Workshop, pp. 57–62, 1972.Google Scholar
- S. Nahar, S. Sahni, and E. Shragowitz, "Simulated Annealing and Combinatorial Optimization," Proc. 23rd Design Automation Conference, pp. 293–299, June 1986.Google Scholar
- Y. G. Saab and V. B. Rao, "Some NP-Complete Problems in the Physical Design of Digital Integrated Circuits," Report UILU-ENG-90-2218, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, June 1990.Google Scholar