Abstract
Hierarchical graph models are a powerful tool for describing VLSI circuits. They combine the representation of a hierarchical decomposition of a circuit with a graph description of its topological structure in terms of components and connections. Structured Graphs are an example of such models. In this paper we consider the graph-theoretic problems of spanning trees and Steiner trees in structured graphs. These have connections with the global routing problems in VLSI circuits.
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References
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© 1991 Springer-Verlag Berlin Heidelberg
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Ancona, M., Bagga, K.S., Bruzzone, E., De Floriani, L., Deogun, J.S. (1991). Structured graph models: An efficient tool for VLSI design. In: Sherwani, N.A., de Doncker, E., Kapenga, J.A. (eds) Computing in the 90's. Great Lakes CS 1989. Lecture Notes in Computer Science, vol 507. Springer, New York, NY. https://doi.org/10.1007/BFb0038508
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DOI: https://doi.org/10.1007/BFb0038508
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