Novel design techniques for RNS systolic VLSI arrays

  • Paruvachi V. R. Raja
Track 5: Circuits And Systems
Part of the Lecture Notes in Computer Science book series (LNCS, volume 507)


This paper presents novel design techniques for Residue Number System based systolic arrays for arithmetic computation useful in digital signal processing applications. Design of a 5-bit pipelined adder is explained with emphasis on the basic systolic cell design, use of clocks, pipeline techniques, simulation, and layout optimization. This pipelined adder can be used to build systolic multipliers, correlators, computational structures for DFT, etc.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • Paruvachi V. R. Raja
    • 1
  1. 1.Department of Computer Science and EngineeringOakland UniversityRochesterUSA

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