Abstract
We consider the 1-dimensional compaction problem when the layout area contains forbidden regions and the layout components are allowed to move across these regions. Assume we are given a feasible layout containing k forbidden regions and n layout components, where the i-th layout component is a rectilinear polygon consisting of v i vertical edges, v=∑ ni=1 v v. We present an algorithm that determines the positions of the layout components resulting in minimum area in O(σlogσ+σnlogn) time with an O((v+k)log k+(v+ σ)log v) preprocessing time. The quantity σ measures the interaction between the layout components and the forbidden regions, σ ≤ vk. We also describe variants of this algorithms that make the running time problem-dependent. Our algorithms make use of an elegant characterization of a layout of minimum area.
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© 1991 Springer-Verlag Berlin Heidelberg
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Hambrusch, S.E., Tu, H.Y. (1991). New algorithms and approaches for 1-dimensional layout compaction. In: Maurer, H. (eds) New Results and New Trends in Computer Science. Lecture Notes in Computer Science, vol 555. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0038188
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DOI: https://doi.org/10.1007/BFb0038188
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