Abstract
Synapse matrices can be considered as basic building blocks for hardware emulators of Artificial Neural Networks. A great number of today's models use weighted sums in partial or fully connected artificial neurons; these computations being efficiently carried out by analog CMOS current-mode circuits. In this communication several alternative analog CMOS multipliers, as basic cells for synapse matrices with dynamically programmable weights, are summarised; and an enhanced implementation of such cells is presented. A chip including a 8×16 multiplier synapse matrix has been manufactured using a conventional 2µm CMOS process. The synaptic weights are dynamically modifiable and temporary memorized as analog voltages in the capacitive gates of MOS transistors. While maintaining simplicity, the basic cell in the matrix preserves the stored weight against input/outputs changes. The designed prototype has a density of 50 synapses per square millimetre, including the circuitry for individual weight actualization of each synapse in the matrix. Some experimental results demonstrating the functionality of the circuit are also reported.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
GOSER,K.;HILLERINGMANN,U;RUECKERT,U.;SCHUMACHER,K.: VLSI technologies for artificial neural networks. IEEE MICRO. December 1989. pp 28–44.
RAMACHER,U.: "Guide lines to VLSI design of neural nets". In: VLSI Design of Neural Networks". pp.1–17. Kluwer Academic Publishers. 1991.
TRELEAVEN,Ph.; PACHECO,M.; VELLASCO,M.: "VLSI architectures for Neural Networks". IEEE Micro, Dec.1989. pp.8–27.
KUB, F.J.; MOON, K.K.; INGHAM, M.A.; LONG, F.M.: "Programmable Analog Vector-Matrix Multiplier". IEEE Journal of Solid State Circuits, vol.25, no.1, Feb.1990, pp.217–214.
ROSSETTO, O.; JUTTEN, C.; HERAULT, J.; KREUZER, I.: "Analog VLSI synaptic matrices as building blocks for neural networks". IEEE Micro, Vol.9, No.6, pp.56–63. 1989.
BORGSTROM, T.;ISMAIL, M.;BIBYK, S.: Programmable current-mode neural network for implementation in analogue MOS VLSI. IEE Proc. vol 137, Pt.G, no.2, April 1990. pp. 175–184.
PELAYO, F; PRIETO, A; PINO, B; ORTEGA, J; MARTIN-SMITH, P.: "Hardware Implementation of a Neuron Model"; 8th Int Symp Applied Informatics, IASTED, Innsbruck, Austria, Acta Press; February 1990.
PELAYO,F.J.; PRIETO,A.; PINO,B.; MARTIN-SMITH,P.: "Analog VLSI implementation of a neural network with competitive learning"; Proc. of the IEEE Celular Neural Network & Applications Workshop, pp. 197–205, Budapest, Dec. 1990.
PRIETO, A.; MARTIN-SMITH, P.; MERELO, J.J.; PELAYO, F.J.; ORTEGA, J.; FERNANDEZ, F.; PINO, B.: "Simulation and hardware implementation of competitive learning neural networks". In: "Statistical Mechanics and Neural Networks". Lectures Notes in Physics 368. pp.189–204. Springer-Verlag. 1990.
VITTOZ,E; OGUEY,M.A.; MAHER,M.A.; NYS,O.; DUKSTRA,E; CHEVROULET,M.: "Anolog storage of adjustable synaptic weights" In: VLSI Design of Neural Networks". pp.48–63. Kluwer Academic Publishers. 1991.
TSIVIDIS, Y.; SATYANARAYANA, S.: "Analogue circuits for variable-synapse electronic neural networks". Electronics Letters. 19th Nov.1987. vol.23, no.24, pp. 1313–1314.
GOSER,K.; HILLERINGMANN,U.; RUECKERT,U.; SCHUMACHER,K.: "VLSI Technologies for Artificial Neural Networks". IEEE Micro. Dec.1989. pp.28–44.
VERLEYSEN, M.; SIRLETTI, B.; VANDEMEULEBROECKE, A.M.; JESPERS, P.G.A.: "Neural Networks for High-Storage Content-Addressable Memory: VLSI Circuit and Learning Algorithm". IEEE Journal of Solid State Circuits, vol.24, no.3, june 1989. pp.562–569.
GRAF H. P.; JACKEL L. D.; HUBBARD W. E. "VLSI Implementation of a Neural Network Model" Computer; Vol. 21, No3, pp.41–49; 1988
MANN, J.; LIPPMANN, R.; GERGERR, B.; RAFFEL, J.: "A self-Organizing Neural Net Chip". Proc. of the IEEE Custom Integrated Conference, Rochester, New York, May 16–19, 1988.
PRANGE,S.J.; KLAR,H.: "Architectures for a Biology-oriented Neuroemulator". In: VLSI Design of Neural Networks". pp.83–102. Kluwer Academic Publishers. 1991.
MURRAY,A.F.; TARASSENKO,L.;REEKIE,H.M.; HAMILTON,A.; BROWNLOW,M.; HURCHER,S.; BAXTER,D.J.: "Pulsed silicon neural networks-following the biological leader". In: VLSI Design of Neural Networks". pp.103–123. Kluwer Academic Publishers. 1991.
MEAD,C.A.: "Analog VLSI and Neural Systems". Addison-Wesley, 1989.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1991 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Pelayo, F.J., Pino, B., A, P., Ortega, J., Fernandez, F.J. (1991). Cmos implementation of synapse matrices with programmable analog weights. In: Prieto, A. (eds) Artificial Neural Networks. IWANN 1991. Lecture Notes in Computer Science, vol 540. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0035907
Download citation
DOI: https://doi.org/10.1007/BFb0035907
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-54537-8
Online ISBN: 978-3-540-38460-1
eBook Packages: Springer Book Archive