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On the construction of optimal time adders

Extended abstract
  • Bernd Becker
  • Reiner Kolla
Contributed Papers Algorithms
Part of the Lecture Notes in Computer Science book series (LNCS, volume 294)

Abstract

In this paper we present the design of a novel optimal time adder: the conditional carry adder. In order to perform addition a tree-like combination of multiplexer cells is used in the carry computation part. We show that, for the complete conditional carry adder, this results in an overall computation time which seems to be substantially shorter than for any other known (optimal time) adder (e.g. carry look ahead adders ([BrKu]) or conditional sum adders ([Sk])).

The second part of this paper contains a uniform approach to the computation of the carry function resulting in seven different classes of optimal time adders. It is shown that the conditional carry adder and the carry look ahead adder are representatives of two different classes. While section 1 defines the conditional carry adder and proposes a realization which is very time efficient, section 2 provides the possibility to compare this choice with other possible realizations and to choose a different design depending e.g. on specific properties of a given technology.

Keywords

Boolean Function Computation Scheme Boolean Expression Regular Layout Transformation Class 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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3. References

  1. [Be]
    B. Becker: ”Efficient Testing of Optimal-Time Adders”, MFCS, Bratislava 1986, Lecture Notes in Comp.Sc. 133, 218–229Google Scholar
  2. [BHKMO]
    B. Becker, G. Hotz, R. Kolla, P. Molitor, H.G. Osthof: ”Hierarchical Design based on a Calculus of Nets”, Proc. 24th ACM/IEEE Design Autom. Conf., Miami, 1987, 649–653Google Scholar
  3. [BeSp]
    B. Becker, U. Sparmann: ”A Uniform Test Approach for RCC-Adders”, T.R., 7/1987, SFB 124, Saarbrücken 1987Google Scholar
  4. [BhHa]
    D. Bhattacharya, J.P. Hayes: ”Fast and Easily testable Implementation of Arithmetic Functions”, FCTS, Wien 1986, 324–329Google Scholar
  5. [BrKu]
    R.P. Brent, H.T. Kung: ”A regular Layout for Parallel Adders”, IEEE Trans. on Comp., C-31, 1982, 260–264Google Scholar
  6. [HBKM]
    G. Hotz, B. Becker, R. Kolla, P. Molitor: ”Ein logisch-topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen”, Informatik: Forschung und Entwicklung 1986 Band 1 und 2 (Springer-Verlag)Google Scholar
  7. [HNS]
    E. Hörbst, M. Nett, H. Schwärtzel: ”VENUS — Ein Enwurf von VLSI-Schaltungen”, Springer-Verlag Berlin Heidelberg New-York Tokyo 1986Google Scholar
  8. [Ho1]
    G. Hotz: ”Zur Reduktionstheorie der booleschen Algebra”, Colloquium über Schaltkreis-und Schaltwerk-Theorie, (1960), Herausgeber: Unger H., Peschel E., Birkhäuser Verlag, 1961Google Scholar
  9. [Ho2]
    G. Hotz: ”Schaltkreistheorie”, Berlin, New York: de Gruyter, 1974Google Scholar
  10. [Ko]
    R. Kolla: ”Spezifikation und Expansion logisch-topologischer Netze”, Dissertation, Universität des Saarlandes, 1987Google Scholar
  11. [Mo]
    P. Molitor: ”Über die Bikategorie der logisch topologischen Netze und ihre Semantik”, Dissertation, Universität des Saarlandes, 1986Google Scholar
  12. [Sk]
    J. Sklansky: ”Conditional sum addition logic”, IRE-EC 9, 226–231 (1960)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Bernd Becker
    • 1
  • Reiner Kolla
    • 1
  1. 1.Fachbereich 10, Universität des SaarlandesSaarbrückenWest Germany

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