Verification of safety critical systems using TTM/RTTL

  • J. S. Ostroff
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 600)


This paper shows how real-time temporal logic can be used for the verification of safety-critical systems. Heuristics are provided that help the designer to construct a proof diagram that either facilitates the presentation of a proof of correctness, or provides a counterexample to indicate the invalidity of the specification that is being checked. The heuristics can be semi-automated using constraint logic programming languages because most of the reasoning does not involve the actual use of temporal logic. The type of reasoning employed in this paper is not limited to finite state systems, but can be used on infinite state systems as well. The heuristics are illustrated using a process control example.


Timed Transition Systems Verification Real-time Temporal Logic 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • J. S. Ostroff
    • 1
  1. 1.Department of Computer ScienceYork UniversityNorth YorkCanada

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