Improved VLSI design for decoding concatenated codes comprising an irreducible cyclic code and a Reed-Solomon Code

Abstract

The concatenation of a Reed-Solomon code with an irreducible cyclic code is used to increase the error correction capabilities on a bursty digital communication channel, in addition to both reduce the complexity and increase the throughput of a VLSI implementation of the decoder. The concept is illustrated with the (2¹⁰—1,k) Reed-Solomon code and the (11, 10, 2) irreducible binary cyclic code (even parity code). We compare the Berlekamp-Massey processors for the (2¹⁰−1, k) Reed-Solomon code alone, and for the concatenation on the other hand. Both Berlekamp-Massey algorithms in the frequency and in the time domain are used for comparisons. The VLSI structures of the data processing units for each algorithm reveals that the concatenation with irreducible cyclic code results in a significant decrease in the physical size of the decoding algorithm's processor for both the time and frequency domain algorithms, and in an increased operating clock frequency with the frequency domain algorithm.